NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 187

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5—Intel
5.14.4.2 Operation
5.14.4.3 CRC Calculation
November 2007
Order Number: 300641-004US
Warning:The current burst may be terminated by either the transmitter or receiver. A
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6300ESB ICH
All other signals on the IDE connector retain their functional definitions during Ultra
ATA/33 operation.
Initial setup programming consists of enabling and performing the proper configuration
of the Intel
Intel
appropriate Synchronous DMA timings.
When ready to transfer data to or from an IDE device, the Bus Master IDE
programming model is followed. Once programmed, the drive and Intel
control the transfer of data through the Ultra ATA/33 protocol. The actual data transfer
consists of three phases, a start-up phase, a data transfer phase, and a burst
termination phase.
The IDE device begins the start-up phase by asserting DMARQ signal. When ready to
begin the transfer, the Intel
signal is asserted, the host controller will drive CS0# and CS1# inactive, DA0–DA2 low.
For write cycles, the Intel
assert DMARDY#, and then drive the first data word and STROBE signal. For read
cycles, the Intel
DMARDY#. The IDE device will then send the first data word and STROBE.
The data transfer phase continues the burst transfers with the data transmitter (Intel
6300ESB ICH - writes, IDE device - reads) providing data and toggling STROBE. Data is
transferred (latched by receiver) on each rising and falling edge of STROBE. The
transmitter may pause the burst by holding STROBE high or low, resuming the burst by
again toggling STROBE. The receiver may pause the burst by deasserting DMARDY#
and resumes the transfers by asserting DMARDY#. The Intel
a burst transaction in order to prevent an internal line buffer over or under flow
condition, resuming once the condition has cleared. It may also pause a transaction
when the current PRD byte count has expired, resuming once it has fetched the next
PRD.
burst termination consists of a Stop Request, Stop Acknowledge and transfer
of CRC data. The Intel
with the IDE device acknowledging by deasserting DMARQ. The IDE device
stops a burst by deasserting DMARQ and the Intel
acknowledges by asserting STOP. The transmitter then drives the STROBE
signal to a high level. The Intel
onto the DD lines and deassert DMACK#. The IDE device will latch the CRC
value on rising edge of DMACK#. The Intel
burst transfer when it needs to service the opposite IDE channel, when a
Programmed I/O (PIO) cycle is executed to the IDE channel currently running
the burst, or upon transferring the last data from the final PRD.
Cyclic Redundancy Checking (CRC-16) is used for error checking on Ultra ATA/33
transfers. The CRC value is calculated for all data by both the Intel
the IDE device over the duration of the Ultra ATA/33 burst transfer segment. This
segment is defined as all data transferred with a valid STROBE edge from DDACK#
assertion to DDACK# deassertion. At the end of the transfer burst segment, the Intel
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6300ESB ICH, this consists of enabling synchronous DMA mode and setting up
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6300ESB ICH and the IDE device for Ultra ATA/33 operation. For the
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6300ESB ICH will tri-state the DD lines, deassert STOP, and assert
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6300ESB ICH may stop a burst by asserting STOP,
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6300ESB ICH will deassert STOP, wait for the IDE device to
6300ESB ICH will assert DMACK# signal. When DMACK#
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6300ESB ICH will then drive the CRC value
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6300ESB ICH will terminate a
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6300ESB ICH
Intel
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6300ESB ICH will pause
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6300ESB I/O Controller Hub
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6300ESB ICH and
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6300ESB ICH
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