NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 547

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NHE6300ESB S L7XJ

Manufacturer Part Number
NHE6300ESB S L7XJ
Description
Manufacturer
Intel
Datasheet

Specifications of NHE6300ESB S L7XJ

Lead Free Status / RoHS Status
Compliant
12—Intel
12.2.17 Offset 14h: NOTIFY_DADDR—Notify Device
November 2007
Order Number: 300641-004US
Bits
Default Value:
7:1
0
Table 456. Offset 14h: NOTIFY_DADDR—Notify Device Address
Note: This register is in the resume well and is reset by RSMRST#.
Device:
®
Offset:
6300ESB ICH
DEVICE_ADDRESS
Address
Reserved
31
14h
00h
Name
This field contains the 7-bit device address received during
the Host Notify protocol of the SMBus 2.0 specification.
Software should only consider this field valid when the
HOST_NOTIFY_STS bit is set to ‘1’.
Reserved.
Description
Attribute:
Function:
Size:
3
Read-Only
8-bit
Intel
®
6300ESB I/O Controller Hub
Access
RO
547
DS

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