NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 563

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

13—Intel
13.1.22 Offset 52h: PC—Power Management Capabilities
13.1.23 Offset 54h: PCS—Power Management Control and
November 2007
Order Number: 300641-004US
15:1
10:9
14:9
Bits
Bits
Default Value:
Default Value:
8:6
2:0
15
1
5
4
3
Table 481. Offset 52h: PC—Power Management Capabilities Register (Audio—
Table 482. Offset 54h: PCS—Power Management Control and Status Register
Lockable:
Lockable:
Note: This register is not affected by the D3
Device:
Device:
®
Offset:
Offset:
Device Specific Initial-
6300ESB ICH
PME Status (PMES)
PME Clock (PMEC)
PME_Support
ization (DSI)
Aux_Current
Version (VS)
Register (Audio—D31:F5)
D31:F5)
Status Register (Audio—D31:F5)
(Audio—D31:F5) (Sheet 1 of 2)
Reserved
Reserved
Reserved
31
52h
C9C2h
No
Name
31
54h
0000h
No
Name
Indicates PME# may be generated from all D states.
Reserved.
Reports 375mA maximum Suspend well current required
when in the D3 cold state.
Indicates that no device-specific initialization is required.
Reserved.
Indicates that PCI clock is not required to generate PME#.
Indicates support for Revision 1.1 of the PCI Power
Management Specification.
This bit is set when the AC’97 controller would normally
assert the PME# signal independent of the state of the
PME_En bit. This bit resides in the resume well.
Reserved.
HOT
Power Well:
Power Well:
Description
Description
Attribute:
Attribute:
Function:
Function:
to D0 transition.
Size:
Size:
5
Read-Only
16-bit
Core
5
Read/Write
16-bit
Resume
Intel
®
6300ESB I/O Controller Hub
Access
Access
R/WC
RO
RO
RO
RO
RO
RO
RO
RO
563
DS