NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 368

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Table 247. ELCR2—Slave Controller Edge/Level Triggered Register (Sheet 2 of 2)
8.5
8.5.1
Table 248. APIC Direct Registers
Intel
DS
368
Bits
Default Value:
3
2
1
0
®
6300ESB I/O Controller Hub
Device:
Offset:
IRQ11 ECL
IRQ10 ECL
IRQ9 ECL
Advanced Interrupt Controller (APIC0)
There are two APICs in the Intel
5). APIC0’s direct registers are assigned with base address FEC0xxxxH; however, only
primary (legacy) PCI device may write to these registers. APIC1’s direct registers are
assigned with base address FEC1xxxxH. To support legacy device/drivers on external
PCI bus used with the Intel
This means external PCI devices may write to the IRQ pin assertion register (either
FEC0_0020H or FEC1_0020H) to generate interrupts from APIC1.
Since the Intel
MCH will translate EOI special cycle to a memory write cycle to EOI register at address
FEC0_0040H and pass it to the Intel
passed to both APIC0 and APIC1 internally.
From the CPU/MCH point of view, it should always use address FEC0xxxxH to access
APIC0 registers and address FEC1xxxxH to access APIC1 registers. APIC1 will not
respond to the CPU/MCU’s access to address FEC0xxxxH, other than the EOI cycle
stated above.
APIC0 also includes an XAPIC_EN config bit. This bit must be set to enable the I/O (x)
APIC extension to the I/O APIC. This allows the extended feature to be disabled if a
problem is found. For APIC1, this extension is always enabled.
APIC Register Map
The APIC is accessed through an indirect addressing scheme. Two registers are visible
by software for manipulation of most of the APIC registers. These registers are mapped
into memory space and are shown in
Reserved
31
4D1h
00h
Name
FEC0_0000h
Address
®
6300ESB ICH does not implement Hub Interface EOI special cycle, the
0 = Edge.
1 = Level.
0 = Edge.
1 = Level.
0 = Edge.
1 = Level.
Reserved.
Index Register
®
Must be 0.
ICHx, APIC1 has an alternate base address, FEC0xxxxH.
®
6300ESB ICH: APIC0 and APIC1 (device29, function
Register
®
Table
6300ESB ICH. This memory write cycle will be
Description
Attribute:
Function:
248.
Size:
0
Read/Write
8-bit
8 bits
Order Number: 300641-004US
Size
Intel
®
6300ESB ICH—8
November 2007
Type
Access
R/W
R/W
R/W
R/W