NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 768

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

20.2.2
Intel
DS
768
Bits
Default Value:
4:3
7
6
5
2
1
0
®
Table 704. BMIS[P,S]—Bus Master IDE Status Register (D31:F2)
6300ESB I/O Controller Hub
Device:
Offset:
Bus Master IDE Active
PRD Interrupt Status
Drive 1 DMA Capable
Drive 0 DMA Capable
BMIS[P,S]—Bus Master IDE Status Register
(D31:F2)
Reserved
Interrupt
(PRDIS)
31
Primary: 02h
Secondary: 0Ah
00h
Name
(ACT)
Error
0 = When this bit is cleared by software, the interrupt is
1 = This bit is set when the host control execution of a PRD
0 = Not Capable.
1 = Capable. Set by device dependent code (BIOS or device
0 = Not Capable
1 = Capable. Set by device dependent code (BIOS or device
Reserved. Returns ’0’.
Software may use this bit to determine if an IDE device has
asserted its interrupt line (IRQ 14 for the Primary channel,
and IRQ 15 for Secondary).
0 = This bit is cleared by software writing a '1' to the bit
1 = Set by the rising edge of the IDE interrupt line,
0 = This bit is cleared by software writing a '1' to the bit
1 = This bit is set when the controller encounters a target
0 = This bit is cleared by the Intel
1 = Set by the Intel
cleared.
that has its PRD_INT bit set.
driver) to indicate that drive 1 for this channel is capable
of DMA transfers, and that the controller has been
initialized for optimum performance. The Intel
ICH does not use this bit. It is intended for systems that
do not attach BMIDE to the PCI bus.
driver) to indicate that drive 0 for this channel is capable
of DMA transfers, and that the controller has been
initialized for optimum performance. The Intel
ICH does not use this bit. It is intended for systems that
do not attach BMIDE to the PCI bus.
position. When this bit is cleared while the interrupt is
still active, this bit will remain clear until another
assertion edge is detected on the interrupt line.
regardless of whether or not the interrupt is masked in
the 8259 or the internal I/O APIC. When this bit is read
as a ‘1’, all data transferred from the drive is visible in
system memory.
position.
abort or master abort when transferring data on PCI.
last transfer for a region is performed, where EOT for that
region is set in the region descriptor. It is also cleared by
the Intel
the Command register. When this bit is read as a ’0’, all
data transferred from the drive during the previous bus
master command is visible in system memory, unless the
bus master command was aborted.
written to the Command register.
®
6300ESB ICH when the Start bit is cleared in
®
6300ESB ICH when the Start bit is
Description
Attribute:
Function:
Size:
®
6300ESB ICH when the
2
Read/Write Clear
8-bit
®
®
Order Number: 300641-004US
6300ESB
6300ESB
Intel
®
6300ESB ICH—20
November 2007
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