NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 545

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

12—Intel
12.2.14 Offset 0Fh: SMBUS_PIN_CTL—SMBUS Pin Control
12.2.15 Offset 10h: SLV_STS—Slave Status Register
November 2007
Order Number: 300641-004US
Bits
Default Value:
7:3
2
1
0
Table 453. Offset 0Fh: SMBUS_PIN_CTL—SMBUS Pin Control Register
Note: This register is in the resume well and is reset by RSMRST#.
Note: This register is in the resume well and is reset by RSMRST#.
Device:
®
Offset:
SMBDATA_CUR_STS
6300ESB ICH
SMBCLK_CUR_STS
SMBCLK_CTL
Register
All bits in this register are implemented in the 64 KHz clock domain. Therefore,
software must poll this register until a write takes effect before assuming that a write
has completed internally.
Reserved
31
0Fh
See Note
Name
Reserved.
This Read/Write bit has a default of 1.
1 = The SMBCLK pin is not overdriven low. The other SMBus
0 = The Intel
This read-only bit has a default value that is dependent on an
external signal level. This pin returns the value on the
SMBDATA pin. It will be ’1’ to indicate high, ’0’ to indicate low.
This allows software to read the current state of the pin.
This read-only bit has a default value that is dependent on an
external signal level. This pin returns the value on the
SMBCLK pin. It will be ’1’ to indicate high, ’0’ to indicate low.
This allows software to read the current state of the pin.
logic controls the state of the pin.
independent of what the other SMB logic would otherwise
indicate for the SMBCLK pin.
®
6300ESB ICH will drive the SMBCLK pin low,
Description
Attribute:
Function:
Size:
3
Read/Write
8-bit
Intel
®
6300ESB I/O Controller Hub
Access
R/W
RO
RO
545
DS