NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 457

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

9—Intel
9.2.2
November 2007
Order Number: 300641-004US
Bits
Default Value:
4:3
7
6
5
Table 349. BMIS[P,S]—Bus Master IDE Status Register
®
Device:
Offset:
6300ESB ICH
Drive 1 DMA Capable
Drive 0 DMA Capable
PRD_INT_STS
BMIS[P,S]—Bus Master IDE Status Register
Reserved
31
Primary: 02h
Secondary: 0Ah
00h
Name
The Intel
execution of a PRD that has its PRD_INT bit set. This bit is
cleared by software writing a 1 to this bit position. When this
bit is cleared, the interrupt is cleared. Note that there is a
small window where the Intel
execution of a PRD, but the interrupt service routine does not
clear this bit until the next PRD has completed. In that case,
there is a small probability that the interrupt associated with
the subsequent PRD is lost. Software must be written to not
break in this case.
0 = Not Capable.
1 = Capable. Set by device dependent code (BIOS or device
0 = Not Capable
1 = Capable. Set by device dependent code (BIOS or device
Reserved. Returns ’0’.
driver) to indicate that drive 1 for this channel is capable
of DMA transfers, and that the controller has been
initialized for optimum performance. The Intel
ICH does not use this bit. It is intended for systems that
do not attach BMIDE to the PCI bus.
driver) to indicate that drive 0 for this channel is capable
of DMA transfers, and that the controller has been
initialized for optimum performance. The Intel
ICH does not use this bit. It is intended for systems that
do not attach BMIDE to the PCI bus.
®
6300ESB ICH sets this bit when it completes
Description
Attribute:
Function:
®
Size:
6300ESB ICH completes
1
Read/Write Clear
8-bit
Intel
®
®
6300ESB
6300ESB
®
6300ESB I/O Controller Hub
Access
R/W
R/W
R/W
457
DS