NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 720

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Table 647. Modem Control Register (MCR) (Sheet 1 of 2)
Intel
DS
720
®
6300ESB I/O Controller Hub
Modem Control Register
MCR
read/write
Bit Number Bit Mnemonic
7:5
4
3
2
1
LOOP
OUT2
OUT1
RTS
0
Address:
Reset State:
Access:
Reserved
Loop Back Test Mode: This bit provides a local Loopback
feature for diagnostic testing of the UART. When LOOP is set to a
logic 1, the following will occur: The transmitter serial output is
set to a logic ’1’ state. The OUT2# signal is forced to a logic ’1’
state. The receiver serial input is disconnected from the pin. The
output of the Transmitter Shift register is “looped back” into the
receiver shift register input. The four modem control inputs
(CTS#, DSR#, DCD#, and RI#) are disconnected from the pins
and the modem control output pins (RTS# and DTR#) are forced
to their inactive state.
The lower four bits of the Modem Control register are connected
to the upper four Modem Status register bits:
In the diagnostic mode, data that is transmitted is immediately
received. This feature allows the processor to verify the transmit
and receive data paths of the UART. The transmit, receive and
modem control interrupts are operational, except the modem
control interrupts are activated by Control register bits, not the
modem control inputs. A break signal may also be transferred
from the transmitter section to the receiver section in loopback
mode.
0 = Normal UART operation
1 = Test mode UART operation
Out2# Signal Control: This bit controls the OUT2# output.
When the OUT2 bit is set, OUT2# is asserted low. When the
OUT2 bit is cleared, OUT2# is deasserted (set high). Outside of
the UART module, the OUT2# signal is used to connect the
UART's interrupt output to the Interrupt Controller unit.
0 = OUT2# signal is '1' , which disables the UART interrupt.
1 = OUT2# signal is ‘0’.
Test Bit: This bit is used only in Loopback test mode. See (LOOP) Above.
Request To Send: This bit controls the Request to Send (RTS#)
output pin. Bit ’1’ affects the RTS# output in a manner identical
to that described below for the DTR bit.
0 = RTS# pin is 1
1 = RTS# pin is 0
• Coming out of the loopback test mode may result in
• DTR = ’1’ forces DSR to a '1'
• RTS = ’1’ forces CTS to a '1'
• OUT1 = ’1’ forces RI to a '1'
• OUT2 = ’1’ forces DCD to a '1'
unpredictable activation of the delta bits (bits 3:0) in the
Modem Status Register (MSR). It is recommended that MSR
be read once to clear the delta bits in the MSR.
Function
Base + 04H
00H
8-bit
Order Number: 300641-004US
Intel
®
6300ESB ICH—19
November 2007