NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 19

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Contents—Intel
9
10
November 2007
Order Number: 300641-004US
IDE Controller Registers (D31:F1) ......................................................................... 435
9.1
9.2
USB UHCI Controllers Registers ............................................................................. 461
10.1
8.10.4 Offset GPIOBASE + 0Ch: GP_LVL—GPIO Level for Input or Output Register.. 427
8.10.5 Offset GPIOBASE + 18h: GPO_BLINK—GPO Blink Enable Register ............... 429
8.10.6 Offset GPIOBASE + 2Ch: GPI_INV—GPIO Signal Invert Register ................. 430
8.10.7 Offset GPIOBASE + 30h:GPIO_USE_SEL2—GPIO Use Select 2 Register........ 431
8.10.8 Offset GPIOBASE + 34h: GP_IO_SEL2—GPIO Input/Output Select 2 Register 432
8.10.9 Offset GPIOBASE + 38h: GP_LVL2—GPIO Level for Input or Output 2 Register ...
PCI Configuration Registers (IDE—D31:F1) ......................................................... 435
9.1.1
9.1.2
9.1.3
9.1.4
9.1.5
9.1.6
9.1.7
9.1.8
9.1.9
9.1.10 Offset 10h - 13h: PCMD_BAR—Primary Command Block
9.1.11 Offset 14h - 17h: PCNL_BAR—Primary Control Block Base
9.1.12 Offset 18h - 1Bh: SCMD_BAR—Secondary Command Block
9.1.13 Offset 1Ch - 1Fh: SCNL_BAR—Secondary Control Block
9.1.14 Offset 20h - 23h: BM_BASE—Bus Master Base Address Register (IDE—D31:F1)..
9.1.15 Offset 24h - 27h: CPBA – IDE Command Posting Base Address................... 444
9.1.16 Offset 2Ch - 2Dh: IDE_SVID—Subsystem Vendor ID
9.1.17 Offset 2Eh - 2Fh: IDE_SID—Subsystem ID (IDE—D31:F1) ......................... 446
9.1.18 Offset 3Ch: INTR_LN—Interrupt Line Register
9.1.19 Offset 3Dh: INTR_PN—Interrupt Pin Register (IDE—D31:F1) ...................... 447
9.1.20 IDE_TIM—IDE Timing Register (IDE—D31:F1).......................................... 447
9.1.21 Offset 44H: SLV_IDETIM—Slave (Drive 1) IDE Timing Register (IDE—D31:F1) ...
9.1.22 Offset 48h: SDMA_CNT—Synchronous DMA Control Register (IDE—D31:F1). 452
9.1.23 Offset 4A - 4Bh: SDMA_TIM—Synchronous DMA Timing Register (IDE—D31:F1) .
9.1.24 IDE_CONFIG—IDE I/O Configuration Register
Bus Master IDE I/O Registers (D31:F1) .............................................................. 455
9.2.1
9.2.2
9.2.3
PCI Configuration Registers (D29:F0/F1) ............................................................ 461
10.1.1 Offset 00 - 01h: VID—Vendor Identification Register
10.1.2 Offset 02 - 03h: DID—Device Identification Register
10.1.3 Offset 04 - 05h: CMD—Command Register
®
6300ESB ICH
432
Base Address Register (IDE—D31:F1) ..................................................... 441
Address Register (IDE—D31:F1)............................................................. 442
Base Address Register (IDE D31:F1) ....................................................... 442
Base Address Register (IDE D31:F1) ....................................................... 443
443
(IDE—D31:F1) ..................................................................................... 445
(IDE—D31:F1) ..................................................................................... 446
451
453
(IDE—D31:F1) ..................................................................................... 455
(USB—D29:F0/F1)................................................................................ 462
(USB—D29:F0/F1)................................................................................ 462
(USB—D29:F0/F1)................................................................................ 463
Offset 00 - 01h: VID—Vendor ID Register (LPC I/F—D31:F1) ..................... 436
Offset 02 - 03h: DID—Device ID Register (LPC I/F—D31:F1)...................... 436
Offset 04h - 05h: CMD—Command Register (IDE—D31:F1) ....................... 437
Offset 06 - 07h: STS—Device Status Register (IDE—D31:F1) ..................... 438
Offset 08h: RID—Revision ID Register (IDE—D31:F1) ............................... 439
Offset 09h: PI—Programming Interface (IDE—D31:F1).............................. 439
Offset 0Ah: SCC—Sub Class Code (IDE—D31:F1) ..................................... 440
Offset 0Bh: BCC—Base Class Code (IDE—D31:F1) .................................... 441
Offset 0Dh: MLT—Master Latency Timer (IDE—D31:F1)............................. 441
BMIC[P,S]—Bus Master IDE Command Register........................................ 456
BMIS[P,S]—Bus Master IDE Status Register ............................................. 457
BMID[P,S]—Bus Master IDE Descriptor Table Pointer Register .................... 459
Intel
®
6300ESB I/O Controller Hub
DS
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