NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 91

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5—Intel
Functional Description
5.1
5.1.1
November 2007
Order Number: 300641-004US
®
Note: The Intel
Note: Poor performing PCI devices that cause long latencies (numerous retries) to Processor-
6300ESB ICH
Hub Interface to PCI Bridge (D30:F0)
The Hub Interface to PCI Bridge resides in PCI Device 30, Function 0 on bus #0. This
portion of the Intel
PCI and the Hub Interface. The arbitration for the PCI bus is handled by this PCI device.
The PCI decoder in this device must decode the ranges for the Hub Interface. All
register contents will be lost when core well power is removed.
PCI Bus Interface
The Intel
Rev. 2.2-compliant implementation. All PCI signals are 5 V tolerant. The Intel
6300ESB ICH integrates a PCI arbiter that supports up to four external PCI bus masters
in addition to the internal Intel
Most transactions targeted to the Intel
PCI bus before being claimed back by the Intel
cycles involving USB, IDE, and AC’97. These transactions will complete over the Hub
Interface without appearing on the external PCI bus. Configuration cycles targeting
USB, IDE or AC’97 will appear on the PCI bus. When the Intel
programmed for positive decode, the Intel
appearing on the external PCI bus in medium decode time. When the Intel
ICH is programmed for subtractive decode, the Intel
cycles in subtractive time. When the Intel
subtractive decode, these cycles may be claimed by another positive decode agent out
on PCI. This architecture enables the ability to boot off of a PCI card that positively
decodes the boot cycles. In order to boot off a PCI card it is necessary to keep the
Intel
BOOT_STS bit (bit 2, TCO2 Status Register) will be set.
When the processor issues a locked cycle to a resource that is too slow (e.g., PCI), the
Intel
completion. This may be critical for isochronous buses which assume certain timing for
their data flow, such as AC’97 or USB. Devices on these buses may suffer from
underrun when the asynchronous traffic is too heavy. Underrun means that the same
data is sent over the bus while the Intel
for the next data. Snoop cycles are not permitted while the processor side bus is
locked.
Locked cycles are assumed to be rare. Locks by PCI targets are assumed to exist for a
short duration (a few microseconds at most). When a system has a very large number
of locked cycles and some that are very long, then the system will definitely experience
underruns and overruns. The units most likely to have problems are the AC’97
controller and the USB controllers. Other units could get underruns/overruns, but are
much less likely. The IDE controller (due to its stalling capability on the cable) should
not get any underruns or overruns.
traffic.
to-PCI Locked cycles may starve isochronous transfers between USB or AC’97 devices
®
®
6300ESB ICH in subtractive decode mode. When booting off a PCI card, the
6300ESB ICH will not allow upstream requests to be performed until the cycle
®
®
6300ESB ICH’s AC’97, IDE and USB Controllers cannot perform peer-to-peer
6300ESB ICH PCI interface provides a 33 MHz, PCI Local Bus Specification,
®
6300ESB ICH implements the buffering and control logic between
®
6300ESB ICH requests.
®
®
6300ESB ICH will first appear on the external
®
6300ESB ICH is not able to issue a request
®
6300ESB ICH is programmed for
6300ESB ICH will claim the cycles
®
6300ESB ICH. The exceptions are I/O
®
6300ESB ICH will claim these
Intel
®
®
6300ESB ICH is
6300ESB I/O Controller Hub
®
6300ESB
®
5
DS
91