NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 659

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

18—Intel
18.6.1.6 Offset 09: CC—Class Code
18.6.1.7 Offset 0C: CLS—Cache Line Size
November 2007
Order Number: 300641-004US
23:1
15:0
07:0
07:0
Bits
Bits
6
8
Table 589. Offset 09: CC—Class Code
Table 590. Offset 0C: CLS—Cache Line Size
Note: This contains the class code, sub class code, and programming interface for the device.
Note: This indicates the cache line size of the system.
Code (BCC)
Code (SCC)
®
Cache Line
Base Class
Programmi
Size (CLS)
Device
Device
Sub Class
Offset
Offset
Interface
6300ESB ICH
Name
Name
(PIF)
ng
28
09
28
0C
The value in this register is used by the Intel
to determine the size of packets on the Hub Interface. This
read/write register specifies the system cache line size in
units of dWords. When the value is ‘08h’, represents a 32-
byte line (8 dWords). A value of ‘10h’ represents a 64-byte
line, and a value of ‘20h’ represents a 128-byte line.
Any value outside this range defaults to a 64-byte line. When
the Intel
to the Hub Interface, this value is used to partition the
requests such that multiple snoops for the same line are
avoided in the memory subsystem.
The value of 06h indicates that this is a bridge device.
8-bit value that indicates this is of type PCI-PCI bridge.
Indicates that this is standard (non-subtractive) PCI-PCI
bridge.
®
6300ESB ICH is creating read and write requests
Description
Description
Attribute:
Attribute:
Function
Function
Size:
Size:
®
6300ESB ICH
0
Read-Only
24-bit
0
Read/Write
8-bit
Intel
®
Reset
Value
Reset
Value
6300ESB I/O Controller Hub
00h
06h
04h
00h
Access
Access
R/W
RO
RO
RO
659
DS