NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 801
NHE6300ESB S L7XJ
Manufacturer Part Number
NHE6300ESB S L7XJ
Description
Manufacturer
Intel
Datasheet
1.NHE6300ESB_S_L7XJ.pdf
(848 pages)
Specifications of NHE6300ESB S L7XJ
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22—Intel
Table 717. IDE PIO and Multiword DMA ModeTiming
November 2007
Order Number: 300641-004US
NOTES:
Sym
1. IORDY is internally synchronized. This timing is to ensure recognition on the next clock.
2. PIORDY sample point from DIOx# assertion and PDIOx# active pulse width is programmable from 2-5 PCI
3. PIORDY sample point from DIOx# assertion, PDIOx# active pulse width and PDIOx# inactive pulse width
4. PDIOx# inactive pulse width is programmable from 1-4 PCI clocks when the drive mode is Mode 2 or greater.
t60
t61
t62
t63
t64
t65
t66
t67
t68
t69
t70
t71
t72
t73
t74
t75
t76
clocks when the drive mode is Mode 2 or greater. Refer to the ISP field in the IDE Timing Register.
cycle time is the compatible timing when the drive mode is Mode 0/1. Refer to the TIM0/1 field in the IDE
timing register.
Refer to the RCT field in the IDE Timing Register.
PDIOR#/PDIOW#/SDIOR#/SDIOW# Active From HICLK
Rising
PDIOR#/PDIOW#/SDIOR#/SDIOW# Inactive From HICLK
Rising
PDA[2:0]/SDA[2:0] Valid Delay From HICLK Rising
PDCS1#/SDCS1#, PDCS3#/SDCS3# Active From HICLK
Rising
PDCS1#/SDCS1#, PDCS3#/SDCS3# Inactive From HICLK
Rising
PDDACK#/SDDACK# Active From HICLK Rising
PDDACK#/SDDACK# Inactive From HICLK Rising
PDDREQ/SDDREQ Setup Time to HICLK Rising
PDDREQ/SDDREQ Hold From HICLK Rising
PDD[15:0]/SDD[15:0] Valid Delay From HICLK Rising
PDD[15:0]/SDD[15:0] Setup Time to HICLK Rising
PDD[15:0]/SDD[15:0] Hold From HICLK Rising
PIORDY/SIORDY Setup Time to HICLK Rising
PIORDY/SIORDY Hold From HICLK Rising
PIORDY/SIORDY Inactive Pulse Width
PDIOR#/PDIOW#/SDIOR#/SDIOW# Pulse Width Low
PDIOR#/PDIOW#/SDIOR#/SDIOW# Pulse Width High
®
6300ESB ICH
Parameter
Min
10
48
2
2
2
2
2
2
2
7
7
2
7
7
7
Max
20
20
30
30
30
20
20
30
Intel
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
®
6300ESB I/O Controller Hub
Notes
2,
3,
1
1
3
4
Figure 50
Figure 51
Figure 50
Figure 51
Figure 50
Figure 50
Figure 50
Figure 51
Figure 51
Figure 51
Figure 50
Figure 51
Figure 50
Figure 51
Figure 50
Figure 51
Figure 50
Figure 50
Figure 50
Figure 50
Figure 51
Figure 50
Figure 51
Figure
801
DS
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