NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 106

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5.3.6
5.3.6.1
5.3.6.2
5.3.6.3
5.4
5.4.1
Intel
DS
106
®
6300ESB I/O Controller Hub
Software Commands
There are three additional special software commands that the DMA controller may
execute. The three software commands are:
They do not depend on any specific bit pattern on the data bus.
Clear Byte Pointer Flip-Flop
This command is executed prior to writing or reading new address or word count
information to/from the DMA controller. This initializes the flip-flop to a known state so
that subsequent accesses to register contents by the microprocessor will address upper
and lower bytes in the correct sequence.
When the Host processor is reading or writing DMA registers, two Byte Pointer flip-flops
are used; one for channels 0–3 and one for channels 4–7. Both of these act
independently. There are separate software commands for clearing each of them (0Ch
for channels 0–3, 0D8h for channels 4–7).
DMA Master Clear
This software instruction has the same effect as the hardware reset. The Command,
Status, Request, and Internal First/Last Flip-Flop Registers are cleared and the Mask
Register is set. The DMA controller will enter the idle cycle.
There are two independent master clear commands; 0Dh which acts on channels 0–3,
and 0DAh which acts on channels 4–7.
Clear Mask Register
This command clears the mask bits of all four channels, enabling them to accept DMA
requests.
I/O port 00Eh is used for channels 0–3 and I/O port 0DCh is used for channels 4–7.
LPC DMA
DMA on LPC is handled through the use of the LDRQ# lines from peripherals and
special encodings on LAD[3:0] from the host. Single, Demand, Verify, and Increment
modes are supported on the LPC interface. Channels 0 – 3 are 8 bit channels. Channels
5 – 7 are 16-bit channels. Channel 4 is reserved as a generic bus master request.
Asserting DMA Requests
Peripherals that need DMA service encode their requested channel number on the
LDRQ# signal. To simplify the protocol, each peripheral on the LPC I/F has its own
dedicated LDRQ# signal (they may not be shared between two separate peripherals).
The Intel
support DMA or bus mastering.
1. Clear Byte Pointer Flip-Flop
2. Master Clear
3. Clear Mask Register
®
6300ESB ICH has two LDRQ# inputs, allowing at least two devices to
Order Number: 300641-004US
Intel
®
6300ESB ICH—5
November 2007