NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 392
NHE6300ESB S L7XJ
Manufacturer Part Number
NHE6300ESB S L7XJ
Description
Manufacturer
Intel
Datasheet
1.NHE6300ESB_S_L7XJ.pdf
(848 pages)
Specifications of NHE6300ESB S L7XJ
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8.8.2
Table 280. APM Register Map
8.8.2.1
Table 281. APM_CNT—Advanced Power Management Control Port Register
8.8.2.2
Table 282. APM_STS—Advanced Power Management Status Port Register
Intel
DS
392
Bits
Bits
Default Value:
Default Value:
7:0
7:0
I/O Address:
I/O Address:
®
6300ESB I/O Controller Hub
Lockable:
Lockable:
Note: Usage: Legacy Only.
Note: Usage: Legacy Only.
Device:
Device:
APM I/O Decode
Table 280
enabled in the PCI Device 31: Function 0 space (APMDEC_EN), and cannot be moved
(fixed I/O location).
APM_CNT—Advanced Power Management Control Port
Register
APM_STS—Advanced Power Management Status Port
Register
Address
31
B2h
00h
No
Name
31
B3h
00h
No
Name
B2h
B3h
shows the I/O registers associated with APM support. This register space is
Mnemonic
APM_CNT
APM_STS
Used to pass an APM command between the OS and the SMI
handler. Writes to this port not only store data in the APMC
register, but also generates an SMI# when the APMC_EN bit
is set.
Used to pass data between the OS and the SMI handler.
Basically, this is a scratchpad register and is not affected by
any other register or function (other than a PCI reset).
Advanced Power Management Control
Advanced Power Management Status
Register Name/Function
Power Well:
Power Well:
Description
Description
Attribute:
Attribute:
Function:
Function:
Size:
Size:
Port
Port
0
Read/Write
8-bit
Core
0
Read/Write
8-bit
Core
Order Number: 300641-004US
Intel
Default
00h
00h
®
6300ESB ICH—8
November 2007
Access
Access
Type
R/W
R/W
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