NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 717

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

19—Intel
Table 645. Line Control Register (LCR) (Sheet 2 of 2)
19.5.1.3.7 Line Status Register (LSR)
November 2007
Order Number: 300641-004US
®
6300ESB ICH
This register provides status information to the processor concerning the data
transfers. Bits 5 and 6 show information about the transmitter section. The rest of the
bits contain information about the receiver.
In non-FIFO mode, three of the LSR register bits, parity error, framing error, and break
interrupt, show the error status of the character that has just been received. In FIFO
mode, these three bits of status are stored with each received character in the FIFO.
LSR shows the status bits of the character at the top of the FIFO. When the character at
the top of the FIFO has errors, the LSR error bits are set and are not cleared until
software reads LSR, even if the character in the FIFO is read and a new character is
now at the top of the FIFO.
Bits 1 through 4 are the error conditions that produce a receiver line status interrupt
when any of the corresponding conditions are detected and the interrupt is enabled.
These bits are not cleared by reading the erroneous byte from the FIFO or receive
buffer. They are cleared only by reading LSR. In FIFO mode, the line status interrupt
Serial Line Control Register
LCR
read/write
Bit Number
1:0
4
3
2
Bit Mnemonic
WLS[1:0]
EPS
PEN
STB
Address:
Reset State:
Access:
Even Parity Select: This bit is the even parity select bit. When
PEN is a logic ’1’ and EPS is a logic ‘0’, an odd number of logic ’1’s
is transmitted or checked in the data word bits and the parity bit.
When PEN is a logic ’1’ and EPS is a logic ‘1’, an even number of
logic ones is transmitted or checked in the data word bits and
parity bit. If PEN = 0, EPS is ignored.
0 = Sends or checks for odd parity.
1 = Sends or checks for even parity.
Parity Enable: This is the parity enable bit. When PEN is a logic
‘1’, a parity bit is generated (transmit data) or checked (receive
data) between the last data word bit and Stop bit of the serial
data. (The parity bit is used to produce an even or odd number of
’1’s when the data word bits and the parity bit are summed.)
0 = No parity function
1 = Allows parity generation and checking.
Stop Bits: This bit specifies the number of stop bits transmitted
and received in each serial character. If STB is a logic ‘0’, one
stop bit is generated in the transmitted data. If STB is a logic ’1’
when a 5-bit word length is selected through bits ’0’ and ‘1’, then
one and one half stop bits are generated. If STB is a logic ’1’
when either a 6, 7, or 8-bit word is selected, then two stop bits
are generated. The receiver checks the first stop bit only,
regardless of the number of stop bits selected.
0 = 1 stop bit
1 = 2 stop bits, except for 5-bit character then 1-1/2 bits
Word Length Select: The Word Length Select bits specify the
number of data bits in each transmitted or received serial
character.
00 = 5-bit character (default)
01 = 6-bit character
10 = 7-bit character
11 = 8-bit character
Base + 03H
00H
8-bit
Function
Intel
®
6300ESB I/O Controller Hub
717
DS