NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 691

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

18—Intel
18.8
18.8.1
Table 620. PCI-X Interface Command Encoding
18.8.2
November 2007
Order Number: 300641-004US
®
6300ESB ICH
PCI-X Interface
This section is not intended to describe the PCI-X protocol. It is intended to clarify the
Intel
interpretation. Please see the PCI-X Addendum to the PCI specification, revision 1.0 for
all details related to PCI-X operation.
Unless otherwise noted in this section, the Intel
PCI-X addendum.
Command Encoding
Attributes
The following table describes how the Intel
the
PCI-X specification leaves some implementation leeway.
000
000
001
001
010
010
011
011
0
1
0
1
0
1
0
1
Type of Transaction
indication is given back on the Hub Interface when a posted PCI write fails on the
Hub Interface – the north Hub Interface agent must handle this condition).
®
Memory Read dWord
6300ESB ICH behavior in areas of the specification which are open to
Memory Write
acknowledge
Special cycle
Reserved
Reserved
Interrupt
I/O write
I/O read
Maste
6300ESB ICH
Yes
Yes
Yes
Yes
No
No
No
No
r
Intel
As
Targe
®
Yes
Yes
No
No
No
No
No
No
t
®
100
100
101
101
110
110
111
111
0
1
0
1
0
1
0
1
6300ESB ICH fills in attribute fields where
Type of Transaction
®
Alias to Memory Write
Alias to Memory Read
6300ESB ICH follows all rules of the
Memory Write Block
Memory Read Block
Configuration Write
Dual Address Cycle
Configuration Read
Split Completion
Block
Block
Intel
®
6300ESB I/O Controller Hub
6300ESB ICH
Mast
Yes
Yes
Yes
Yes
Yes
No
No
No
er
Intel
As
Targe
®
Yes
Yes
Yes
Yes
Yes
Yes
No
No
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