NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 671

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

18—Intel
18.6.1.22Offset 40: CNF—Intel
November 2007
Order Number: 300641-004US
14:1
Bits
15
09
08
0
Table 605. Offset 40: CNF—Intel® 6300ESB I/O Controller Hub Configuration
PCI-X Mode
®
Granularity
PXPCLKOU
Enable I/O
Device
Offset
Reserved
(PMODE)
Space to
(DPCLK)
Disable
6300ESB ICH
(EN1K)
Name
T 4- 0
1K
Configuration
(Sheet 1 of 3)
28
40
Reserved.
Disables a PCI-X clock output that is not used in the system.
Bit 10 refers to PCLKOUT0, bit 11 to PCLKOUT1, etc. When
disabled, the PCLKOUT pin is tri-stated.
NOTE: Bit 14 controls the feedback path. This bit should not
When set, this enables the I/O space to be decoded to 1K,
down from the 4K limit that currently exists in the I/O base
and limit registers. It does this by redefining bits [11:10] and
bits [3:2] of the IOBL register at offset 1C to be read/write
and enables them to be compared with I/O address bits
[11:10] to determine if they are within the bridge's I/O
range.
When set, indicates the bus is operating in PCI-X mode. When
cleared, indicates the bus is in PCI mode. The power up value
of this register is written based upon the table below:
PCIXCAP=Bit 7 M66EN=Bit 6
The default value (S-select value) is determined by the values
of M66EN and PCIXCAP pins as per the table above.
NOTE: This register should not be written to and should be
PCIXCAP M66EN
Mid
0
0
1
be written to a ‘1’.
treated by Software as Read Only. Writes will change
the register value rendering the contents invalid since
the value will not affect the PCI-X Mode.
N/A
N/A
0
1
PCI/XFreq PMODE
PCI-X 66 MHz
PCI-X 66 MHz
Description
PCI
PCI
®
33 MHz
66 MHz
6300ESB I/O Controller Hub
Attribute:
Function
Size:
0
1
1
0
0
Read/Write
16-bit
Intel
®
Reset
Value
6300ESB I/O Controller Hub
00h
0
0
Access
R/W
R/W
R/W
RO
671
DS