NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 277

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

6—Intel
Figure 28. Intel
6.2
November 2007
Order Number: 300641-004US
®
6300ESB ICH
PCI Configuration Map
Each PCI function on the Intel
The register map tables for each function are included at the beginning of each
respective chapter.
Configuration Space registers are accessed through configuration cycles on the PCI bus
by the Host bridge using configuration mechanism #1 detailed in the PCI Local Bus
Specification, Revision 2.2.
Some PCI registers contain “Reserved” bits. Software must deal correctly with fields
that are reserved. On reads, software must use appropriate masks to extract the
defined bits and not rely on reserved bits being any particular value. On writes,
software must ensure that the values of reserved bit positions are preserved. That is,
the values of reserved bit positions must first be read, merged with the new values for
other bit positions and then written back. Note the software does not need to perform
read, merge, write operation for the Configuration Address Register (0xCF8h).
USB Classic Host
Bus0:Dev29:F0,1
W atch Dog Timer
Bus0:Dev31:F2
Bus0:Dev29:F5
Bus0:Dev31:F1
Bus0:Dev31:F5
Bus0:Dev29:F4
Bus0:Dev31:F6
Bus0:Dev29:F7
AC’97 Audio
AC’97 Modem
®
USB2 Host
IOxAPIC
SATA
6300ESB ICH Device Diagram
IDE
Physical and
Logical Connection
HubLink Bus 0
®
PCI - LPC Bridge
Bus0:Dev31:F0
Bus0:Dev31:F3
6300ESB ICH has a set of PCI configuration registers.
SMBus Cntrl
LPC Bus
Logical Connection
Only
Bus 0 – Dev30:F0
PCI Bridge
HubLink to
Legacy PCI Bus
Intel
®
6300ESB I/O Controller Hub
Bus 0 – Dev28:F0
Physical Connection
Only
PCI - X Bridge
HubLink to
PCI - X Bus
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