NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 244

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Table 123. Process Call Protocol with PEC (Sheet 2 of 2)
Intel
DS
244
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6300ESB I/O Controller Hub
Block Read/Write
The Intel
be enabled by setting bit ‘1’ of the Auxiliary Control register at offset 0Dh in I/O space,
as opposed to a single byte of buffering. This 32-byte buffer is filled with write data
before transmission, and filled with read data on reception. In the Intel
the interrupt is generated only after a transmission or reception of 32 bytes, or when
the entire byte count has been transmitted/received.
This requires the Intel
count field is transmitted but ignored by the hardware as software will end the transfer
after all bytes it cares about have been sent or received.
For a Block Write software must either force the I2C_EN bit or both the PEC_EN and
AAC bits to 0 when running this command.
SMBus mode: The block write begins with a slave address and a write condition. After
the command code the Intel
more bytes will follow in the message. When a slave had 20 bytes to send, the first
byte would be the number 20 (14h), followed by 20 bytes of data. The byte count may
not be 0. A Block Read or Write is allowed to transfer a maximum of 32 data bytes.
When programmed for a block write command, the Transmit Slave Address, Device
Command, and Data0 (count) registers are sent. Data is then sent from the Block Data
Byte register; the total data sent being the value stored in the Data0 Register. On block
read commands, the first byte received is stored in the Data0 register, and the
remaining bytes are stored in the Block Data Byte register.
The format of the Block Read/Write protocol is shown in
20–27
29–36
39–45
48–55
57–64
66–73
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Bit
19
28
37
38
46
47
56
65
74
75
6300ESB ICH contains a 32-byte buffer for read and write data which may
®
Acknowledge from slave
Acknowledge from slave
Acknowledge from slave
Slave Address - 7 bits
Acknowledge from slave
Acknowledge
Acknowledge
PEC from slave
NOT acknowledge
Stop
Data byte Low - 8 bits
Data Byte High - 8 bits
Repeated Start
Read
Data Byte Low from slave - 8 bits
Data Byte High from slave - 8 bits
6300ESB ICH to check the byte count field. Currently, the byte
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6300ESB ICH issues a byte count describing how many
Description
Table 124
Order Number: 300641-004US
and
Intel
®
®
Table
6300ESB ICH,
6300ESB ICH—5
November 2007
125.