NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 274

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5.20.8
Intel
DS
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6300ESB I/O Controller Hub
The codec will do this by indicating that status data is valid in its TAG, then echo the
read address in slot 1 followed by the read data in slot 2.
The new function of the Intel
contains the read return data, and to set new bits in the new register indicating which
AC_SDIN line the register read data returned on. When it returned on AC_SDIN0, bits
[1:0] contain the value ‘00’. When it returned on AC_SDIN1, the bits contain the value
‘01’, etc.
Intel
returned from a function 5 read. No special command is necessary to cause the bits to
be set. The new driver/BIOS software will read the bits from this register when it cares
to, and may ignore it otherwise. When software is attempting to establish the codec-to-
AC_SDIN mapping, it will single feed the read request and not pipeline to ensure it gets
the right mapping, hardware cannot ensure the serialization of the access.
Software Mapping of AC_SDIN to DMA Engine
Once software has performed the register read to determine codec-to-AC_SDIN
mapping, it will then either set bits [5:4] or [7:6] in the SDATA_IN MAP register to map
this codec to the DMA engine. After it maps the audio codecs, it will set the “SE” (steer
enable) bit, which now lets the hardware know to no longer OR the AC_SDIN lines, and
to use the mappings in the register to steer the appropriate AC_SDIN line to the correct
DMA engines.
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6300ESB ICH hardware may set these bits every time register read data is
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6300ESB ICH hardware is to notice which AC_SDIN line
Order Number: 300641-004US
Intel
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6300ESB ICH—5
November 2007