NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 182

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5.14.3
5.14.3.1 Physical Region Descriptor Format
Figure 16. Physical Region Descriptor Table Entry
Intel
DS
182
®
6300ESB I/O Controller Hub
Bus Master Function
The Intel
Two PCI Bus master channels are provided, one channel for each IDE connector
(primary and secondary). By performing the IDE data transfer as a PCI Bus master, the
Intel
multitasking environments.
programmed for bus master transfers, but only one device per connector may be active
at a time.
The physical memory region to be transferred is described by a Physical Region
Descriptor (PRD). The PRDs are stored sequentially in a Descriptor Table in memory.
The data transfer proceeds until all regions described by the PRDs in the table have
been transferred. Note that the Intel
support memory regions or descriptor tables located on ISA.
Descriptor Tables must not cross a 64-Kbyte boundary. Each PRD entry in the table is 8
bytes in length. The first 4 bytes specify the byte address of a physical memory region.
This memory region must be DWORD aligned and must not cross a 64-Kbyte boundary.
The next two bytes specify the size or transfer count of the region in bytes (64-Kbyte
limit per region). A value of zero in these two bytes indicates 64 Kbytes (thus the
minimum transfer count is 1). When bit 7 (EOT) of the last byte is a 1, it indicates that
this is the final PRD in the Descriptor table. Bus master operation terminates when the
last descriptor has been retired.
When the Bus Master IDE controller is reading data from the memory regions, bit 1 of
the Base Address is masked and byte enables are asserted for all read transfers. When
writing data, bit 1 of the Base Address is not masked and if set, will cause the lower
WORD byte enables to be deasserted for the first DWORD transfer. The write to PCI will
typically consist of a 32-byte cache line. When valid data ends prior to end of the cache
line, the byte enables will be deasserted for invalid data.
The total sum of the byte counts in every PRD of the descriptor table must be equal to
or greater than the size of the disk transfer request. When greater than the disk
transfer request, the driver must terminate the bus master transaction (by setting bit 0
in the Bus Master IDE Command Register to zero) when the drive issues an interrupt to
signal transfer completion.
®
6300ESB ICH off-loads the processor and improves system performance in
®
6300ESB ICH may act as a PCI Bus master on behalf of an IDE slave device.
EOT
Memory Region Physical Base Address [31:1]
Byte 3
Reserved
Byte 2
Both devices attached to a connector may be
Byte Count [15:1]
Byte 1
®
6300ESB ICH bus master IDE function does not
Byte 0
0
0
Order Number: 300641-004US
Main Memory
Memory
Region
Intel
051910_3.drw
®
6300ESB ICH—5
November 2007