NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 731

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

19—Intel
19.8.3.1 Global Control/Configuration Registers [00h — 2Fh]
Table 656. Global Control Registers
19.8.3.2 Logical Device Configuration Registers [30h — FFh]
November 2007
Order Number: 300641-004US
®
6300ESB ICH
The chip-level (global) registers lie in the address range [00h-2Fh]. The design MUST
use all 8 bits of the ADDRESS Port for register selection. All unimplemented registers
and bits ignore writes and return ’0’ when read.
The INDEX PORT is used to select a configuration register in the chip. The DATA PORT is
then used to access the selected register. These registers are accessible only in the
Configuration Mode.
Used to access the registers that are assigned to each logical unit. This chip supports
two logical units and has two sets of logical device registers. The two logical devices are
UART0 and UART1. A separate set (bank) of control and configuration registers exists
for each logical device and is selected with the Logical Device # Register.
The INDEX PORT is used to select a specific logical device register. These registers are
then accessed through the DATA PORT.
The Logical Device registers are accessible only when the device is in the Configuration
State. The logical register addresses are shown in
Logical Device #
Default = 00h
Device ID
Default = 00h
Device Rev
Default = 01h
SIU Interface
Default = 01h
SIU Configuration
Default = 02h
Register
(R/W bits 7:2,
(R/W bits 3:2,
Address
R- bit 1)
R- bit 1)
(Type)
(R/W)
07h
20h
21h
28h
29h
(R)
(R)
0
0
Logical Device Select: A write to this register selects the
current logical device. This allows access to the control and
configuration registers for each logical device.
Device ID: A read only register which provides the Device
ID.
Device Rev: A read only register which provides device
revision information.
Bit 1 – LPC bus wait states
1 = Long wait states (sync 6)
0 = Not supported
Bit 7:2, 0 – RSVD = 0
Bit 0 – SIRQ enable
1 = Enabled; participates in interrupt generation
0 = Disabled; serial interrupts disabled
Bit 1 – IRQ mode (Read only, Writes ignored)
1 = Continuous mode
0 = Quiet mode
Bit 3:2 – UART_CLK pre-divide UART_CLK input
00
01
10
11
Bit 7:4 – RSVD = 0
Divide by 1
Divide by 8
Divide by 26
Reserved
Table 657
Description
Intel
through
®
6300ESB I/O Controller Hub
Table
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731
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