NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 120

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5.6.7
Figure 13. Port 60 Read Clearing IRQ1 AND IRQ12 Latch
Intel
DS
120
®
6300ESB I/O Controller Hub
sensitive mode. The Intel
an active high level to the PIC. When a PCI interrupt is routed onto the PIC, the
selected IRQ may no longer be used by an ISA device (through SERIRQ). However,
active low non-ISA interrupts may share their interrupt with PCI interrupts.
Internal sources of the PIRQs, including SCI and TCO interrupts, cause the external
PIRQ to be asserted. The Intel
other external sources, and routes it accordingly.
Special Handling of IRQ1 and IRQ12
IRQ1 and IRQ12 interrupts are treated in a slightly different fashion from other
interrupts in the system. In a legacy PC environment, these interrupts were not held
active until serviced, but rather pulsed whenever a key or button was pressed. In
newer systems, this pulsing is no longer done. However, the Intel
still handle old keyboard controllers which perform the pulse operation. Therefore, the
Intel
so required.
Two register bits in configuration register D0h in function 0 enable the latching of IRQ1
and 12. IRQ1 may optionally be latched through bit 12, and IRQ12 may optionally be
latched through bit 11. When these bits are set, the corresponding interrupt is held to
the 8259 until an I/O read from port 60 is seen. The port 60 read is an indication to the
keyboard controller that the interrupt has been serviced.
Another item to note is that on previous components (ICHx), it was always ensured
that the keyboard controller would exist behind the Intel
bus. On Intel
must be done through a snoop of port 60h. The waveform which performs this snoop is
shown in
only one PCI clock wide. This cannot be a handshake signal because the Intel
6300ESB ICH is not necessarily responding to the cycle.
port60read
FRAME#
PCICLK
®
TRDY#
C/BE#
IRDY#
6300ESB ICH contains logic which may sample and hold these interrupts when
AD
Figure
0ns
®
6300ESB ICH, this is not the case. Therefore, the clearing of the latch
13. Note that the signal which indicates that a port 60 read occurred is
60
2
50ns
®
6300ESB ICH will internally invert the PIRQx# line to send
®
6300ESB ICH receives the PIRQ input, like all of the
100ns
E
150ns
®
6300ESB ICH on the ISA
200ns
Order Number: 300641-004US
Data
®
Intel
6300ESB ICH must
®
6300ESB ICH—5
250ns
November 2007
®
3