NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 518

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Table 420. PORTSC- Port N Status and Control (Sheet 1 of 4)
Intel
DS
518
31:2
19:1
15:1
Bits
Default Value:
22
21
20
13
12
3
6
4
®
6300ESB I/O Controller Hub
Wake on Connect Enable
Device:
Offset:
Enable (WKDSCNNT_E)
Wake on Over-current
Wake on Disconnect
Enable (WKOC_E)
Port Test Control
Port Power (PP)
(WKCNNT_E)
Port Owner
Reserved
Reserved
29
Port 0:CAPLENGTH+44-47h
Port 1: CAPLENGTH+48-4Bh
Port 2: CAPLENGTH+4C-4Fh
Port 3: CAPLENGTH+50-53h
00003000h
Name
Reserved. These bits are reserved for future use and will
return a value of ’0’ when read.
Default = 0b. Writing this bit to a ’1’ enables the setting of
the PME Status bit in the Power Management Control/Status
Register (offset 54, bit 15) when the Over-current Active bit
(bit 4 of this register) is set.
Default = 0b. Writing this bit to a ’1’ enables the setting of
the PME Status bit in the Power Management Control/Status
Register (offset 54, bit 15) when the Current Connect Status
changes from connected to disconnected (i.e., bit ’0’ of this
register changes from ’1’ to ‘0’).
Default = 0b. Writing this bit to a ’1’ enables the setting of
the PME Status bit in the Power Management Control/Status
Register (offset 54, bit 15) when the Current Connect Status
changes from disconnected to connected (i.e., bit ’0’ of this
register changes from ’0’ to ‘1’).
NOTE: This feature is not supported.
Default = 0000b. When this field is ’0’, the port is NOT
operating in a test mode. A non-’0’ value indicates that it is
operating in test mode and the specific test mode is indicated
by the specific value. The encoding of the test mode bits is
(0110b - 1111b are reserved):
Bits
0000b
0001b
0010b
0011b
0100b
0101b
Refer to Chapter 7 of the USB Specification, Revision 2.0, for
details on each test mode.
Should be written to =00b; other values will result in
unspecified behavior.
Default = 1b. This bit unconditionally goes to a ’0’ when the
Configured Flag bit makes a ’0’ to ’1’ transition.This bit
unconditionally goes to 1b whenever the Configure Flag bit is
’0’
System software uses this field to release ownership of the
port to a selected host controller in the event that the
attached device is not a high-speed device. Software writes a
’1’ to this bit when the attached device is not a high-speed
device. A ’1’ in this bit means that a companion host
controller owns and controls the port. See Section 4 of the
EHCI Specification for operational details.
Read-only with a value of ‘1’. This indicates that the port does
have power.
Test Mode
Test mode not enabled
Test J_STATE
Test K_STATE
Test SE0_NAK
Test Packet
Test FORCE_ENABLE
Description
Attribute:
Function:
Size:
7
Read/Write
32-bit
Order Number: 300641-004US
Intel
®
6300ESB ICH—11
November 2007
Access
R/W
R/W
R/W
R/W
R/W
R/W
RO