NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 108

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5.4.3
5.4.4
5.4.5
5.4.6
Intel
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6300ESB I/O Controller Hub
General Flow of DMA Transfers
Arbitration for DMA channels is performed through the 8237 within the host. Once the
host has won arbitration on behalf of a DMA channel assigned to LPC, it asserts
LFRAME# on the LPC I/F and begins the DMA transfer. The general flow for a basic DMA
transfer is as follows:
Terminal Count (TC)
Terminal count is communicated through LAD[3] on the same clock that DMA channel is
communicated on LAD[2:0]. This field is the CHANNEL field. Terminal count indicates
the last byte of transfer, based upon the size of the transfer.
For example, on an eight bit transfer size (SIZE field is ‘00b’), when the TC bit is set,
this is the last byte. On a 16 bit transfer (SIZE field is ‘01b’), when the TC bit is set, the
second byte is the last byte. The peripheral, therefore, must internalize the TC bit when
the CHANNEL field is communicated, and only signal TC when the last byte of that
transfer size has been transferred.
Verify Mode
Verify mode is supported on the LPC interface. A verify transfer to the peripheral is
similar to a DMA write, where the peripheral is transferring data to main memory. The
indication from the host is the same as a DMA write, so the peripheral will be driving
data onto the LPC interface. However, the host will not transfer this data into main
memory.
DMA Request Deassertion
An end of transfer is communicated to the Intel
field transmitted by the peripheral. An LPC device must not attempt to signal the end of
a transfer by deasserting LDREQ#. When a DMA transfer is several bytes, such as a
transfer from a demand mode device, the Intel
deassert the DMA request based on the data currently being transferred.
1. The Intel
2. The Intel
3. The Intel
4. The Intel
5. When a DMA read…
6. When a DMA write…
7. The peripheral turns around the bus.
LFRAME# asserted.
transfer direction.
count.
— The Intel
— The peripheral acknowledges the data with a valid SYNC.
— When a 16 bit transfer, the process is repeated for the next 8 bits.
— The Intel
— The peripheral indicates data ready through SYNC and transfers the first byte.
— When a 16 bit transfer, the peripheral indicates data ready and transfers the next byte.
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6300ESB ICH starts transfer by asserting ‘0000b’ on LAD[3:0] with
6300ESB ICH asserts ‘cycle type’ of DMA, direction based on DMA
6300ESB ICH asserts channel number and, when applicable, terminal
6300ESB ICH indicates the size of the transfer: 8 or 16 bits.
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6300ESB ICH drives the first 8 bits of data and turns the bus around.
6300ESB ICH turns the bus around and waits for data.
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6300ESB ICH needs to know when to
6300ESB ICH through a special SYNC
Order Number: 300641-004US
Intel
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6300ESB ICH—5
November 2007