NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 514

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

11.2.2.3 Offset CAPLENGTH + 08 - 0Bh: USB EHCI INTR—USB
Table 414. Offset CAPLENGTH + 08 - 0Bh: USB EHCI INTR—USB EHCI Interrupt
11.2.2.4 Offset CAPLENGTH + 0C - 0Fh: FRINDEX—Frame Index
Intel
DS
514
NOTES:
31:6
1. For all enable register bits, 1= Enabled, 0= Disabled.
2. This register enables and disables reporting of the corresponding interrupt to the software. When a bit is set
Bits
Default Value:
5
4
3
2
1
0
and the corresponding interrupt is active, an interrupt is generated to the host. Interrupt sources that are
disabled in this register still appear in the Status Register to allow the software to poll for events. Each
interrupt enable bit description indicates whether it is dependent on the interrupt threshold mechanism (see
Section 4 of the EHCI Specification), or not.
®
6300ESB I/O Controller Hub
Note: This register is used by the host controller to index into the periodic frame list. The
Device:
Offset:
Port Change Interrupt
USB Interrupt Enable
USB Error Interrupt
Frame List Rollover
Interrupt on Async
Host System Error
Advance Enable
EHCI Interrupt Enable
Enable
register updates every 125 microseconds (once each micro-frame). Bits [12:3] are
used to select a particular entry in the Periodic Frame List during periodic schedule
execution. The number of bits used for the index is fixed at 10 for the Intel
ICH since it only supports 1024-entry frame lists. This register must be written as a
Reserved
Enable
Enable
Enable
Enable
29
CAPLENGTH + 08-0Bh
00000000h
Name
Reserved.These bits are reserved and should be ’0’.
When this bit is a ’1’ and the Interrupt on Async Advance bit
in the USBSTS register is a ’1’, the host controller will issue an
interrupt at the next interrupt threshold. The interrupt is
acknowledged by software clearing the Interrupt on Async
Advance bit.
When this bit is a ’1’ and the Host System Error Status bit in
the USBSTS register is a ’1’, the host controller will issue an
interrupt. The interrupt is acknowledged by software clearing
the Host System Error bit.
When this bit is a ’1’ and the Frame List Rollover bit in the
USBSTS register is a ’1’, the host controller will issue an
interrupt. The interrupt is acknowledged by software clearing
the Frame List Rollover bit.
When this bit is a ’1’ and the Port Change Detect bit in the
USBSTS register is a ’1’, the host controller will issue an
interrupt. The interrupt is acknowledged by software clearing
the Port Change Detect bit.
When this bit is a ’1’ and the USBERRINT bit in the USBSTS
register is a ’1’, the host controller will issue an interrupt at
the next interrupt threshold. The interrupt is acknowledged
by software by clearing the USBERRINT bit in the USBSTS
register.
When this bit is a ’1’ and the USBINT bit in the USBSTS
register is a ’1’, the host controller will issue an interrupt at
the next interrupt threshold. The interrupt is acknowledged
by software by clearing the USBINT bit in the USBSTS
register.
Description
Attribute:
Function:
Size:
7
Read/Write
32-bit
Order Number: 300641-004US
Intel
®
6300ESB ICH—11
November 2007
®
Access
6300ESB
R/W
R/W
R/W
R/W
R/W
R/W