NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 568

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Table 484. Native Audio Bus Master Control Registers (Sheet 3 of 3)
13.2.1
13.2.2
Intel
DS
568
31:3
Bits
Default Value:
2:0
I/O Address:
®
Table 485. x_BDBAR—Buffer Descriptor Base Address Register
6300ESB I/O Controller Hub
Lockable:
Note: Internal reset as a result of D3
Note: Software may read the register at offset 00h by performing a single 32-bit read from
Note: Software may read the registers at offsets 04h, 05h and 06h simultaneously by
Device:
Buffer Descriptor Base
Address[31:3]
except the registers shared with the AC’97 Modem (GCR, GSR, CASR). Resume well
registers will not be reset by the D3
Core Well registers and bits NOT reset by the D3
Resume Well registers and bits will NOT be reset by the D3
x_BDBAR—Buffer Descriptor Base Address
Register
address offset 00h. Reads across dWord boundaries are not supported.
x_CIV—Current Index Value Register
performing a single 32-bit read from address offset 04h. Software may also read this
register individually by doing a single 8-bit read to offset 04h. Reads across dWord
boundaries are not supported.
68-69h
Offset
•
•
•
•
31
NABMBAR + 00h (PIBDBAR), NABMBAR +
10h (POBDBAR), NABMBAR + 20h
(MCBDBAR), MBBAR + 40h (MC2BDBAR),
MBBAR + 50h (PI2BDBAR), MBBAR + 60h
(SPBAR)
00000000h
No
Name
6Ah
6Bh
80h
Offset 2Ch-2Fh – bits[15,6:0] Global Control (GLOB_CNT)
Offset 30h-33h – bits[29,15,11:10,0] Global Status (GLOB_STA)
Offset 34h – Codec Access Semaphore Register (CAS)
Offset 30h-33h – bits[17:16] Global Status (GLOB_STA)
Mnemonic
SP_PICB
SP_PIV
SP_CR
SDM
These bits represent address bits 31:3. The data should be
aligned on 8 byte boundaries. Each buffer descriptor is 8
bytes long, and the list may contain a maximum of 32
entries.
Hardwired to ‘0’.
S/PDIF Position In Current Buffer
S/PDIF Prefetched Index Value
S/PDIF Control Register
SData_IN Map
HOT
to D0 transition will reset all the core well registers
HOT
Description
to D0 transition.
Name
Power Well:
Attribute:
Function:
HOT
Size:
to D0 transition:
5
Read/Write
32-bit
Core
HOT
to D0 transition:
Order Number: 300641-004US
Intel
Default
0000h
00h
00h
00h
®
6300ESB ICH—13
November 2007
Access
R/W
Access
R/W
R/W
RO
RO