NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 645

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

17—Intel
November 2007
Order Number: 300641-004US
Bits
Default Value:
16
15
14
13
12
11
Table 581. Redirection Table (Sheet 2 of 3)
Device:
®
Offset:
6300ESB ICH
Interrupt Input Pin
Destination Mode
Delivery Status
Trigger Mode
Remote IRR
Polarity
29
10h-11h (vector 0)
through
3E-3Fh (vector 23)
Bit 16-1, Bits[15:12]=0.
All other bits undefined
Name
Mask
0 = Not masked: An edge or level on this interrupt pin results
1 = Masked: Interrupts are not delivered nor held pending.
This field indicates the type of signal on the interrupt pin that
triggers an interrupt.
0 = Edge triggered.
1 = Level triggered.
This bit is used for level-triggered interrupts in Fixed or
Lowest Priority Delivery Modes only; its meaning is undefined
for edge triggered interrupts. For level-triggered interrupts,
this bit is set if the I/O APIC successfully sends the level
interrupt message. Remote IRR bit is reset when an EOI
message is received that matches the interrupt vector in this
entry. This bit is never set for SMI, NMI, INIT, or ExtINT
delivery modes.
This bit specifies the polarity of each interrupt signal
connected to the interrupt pins.
0 = Active high.
1 = Active low.
This field contains the current status of the delivery of this
interrupt. Writes to this bit have no effect.
0 = Idle. No activity for this interrupt.
1 = Pending. Interrupt has been injected, but delivery is held
This field determines the interpretation of the Destination
field.
0 = Physical. Destination APIC ID is identified by bits [59:56].
1 = Logical. Destinations are identified by matching bit
in the delivery of the interrupt to the destination.
Setting this bit after the interrupt is accepted by a local
APIC has no effect on that interrupt. This behavior is
identical to the device withdrawing the interrupt before it
is posted to the processor. It is software's responsibility
to deal with the case where the mask bit is set after the
interrupt message has been accepted by a local APIC unit
but before the interrupt is dispensed to the processor.
up due to the APIC bus being busy or the inability of the
receiving APIC unit to accept the interrupt at this time.
[63:56] with the Logical Destination in the Destination
Format Register and Logical Destination Register in each
Local APIC.
Description
Attribute:
Function:
Size:
5
Read/Write
64 bits each, accessed as two 32 bit
quantities
Intel
®
6300ESB I/O Controller Hub
Access
R/W
R/W
R/W
R/W
R/W
RO
645
DS