NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 250

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5.19.4.2 Bus Time Out (Intel
5.19.5
Table 128. Enable for SMBALERT#
Table 129. Enables for SMBus Slave Write and SMBus Host Events
Intel
DS
250
Slave Write to Wake/
SMI# Command
Slave Write to
SMLINK_SLAVE_SMI
Command
Any combination of
Host Status Register
[4:1] asserted
SMBALERT#
asserted low
(always reported in
Host Status
Register, Bit 5)
®
6300ESB I/O Controller Hub
Event
Event
The Intel
determine whether to enable the counter for the high time of the clock. While the bus is
still low, the high time counter must not be enabled. Similarly, the low period of the
clock may be stretched by an SMBus master when it is not ready to send or receive
data.
When there is an error in the transaction, such that an SMBus device does not signal an
acknowledge, or holds the clock lower than the allowed time-out time, the transaction
will time out. The Intel
The time out minimum is 25 ms. The time-out counter inside the Intel
will start after the last bit of data is transferred by the Intel
waiting for a response. The 25 ms will be a count of 800 RTC clocks.
Interrupts/SMI#
The Intel
the system may alternatively be set up to generate SMI# instead of an interrupt, by
setting the SMBUS_SMI_EN bit.
Table 129
control the generation of the interrupt, Host and Slave SMI, and Wake internal signals.
The rows in the tables are additive, which means that when more than one row is true
for a particular scenario then the results for all of the activated rows will occur.
Register, Offset
INTREN (Host
INTREN (Host Control
Control I/O
®
02h, Bit 0)
I/O Register, Offset
®
and
6300ESB ICH must monitor the SMBus clock line after it releases the bus to
6300ESB ICH SMBus controller uses PIRQB# as its interrupt pin. However,
02h, Bit 0)
X
X
1
Table 130
X
X
0
1
1
®
6300ESB ICH will discard the cycle, and set the DEV_ERR bit.
specify how the various enable bits in the SMBus function
SMB_SMI_EN (Host
D31:F3:Offset 40h,
Configuration
®
Register,
D31:F3:Offset 40h, Bit1)
Configuration Register,
Bit 1)
6300ESB ICH as SMBus Master)
SMB_SMI_EN (Host
X
1
0
X
X
X
0
1
(Slave Command I/
O Register, Offset
SMBALERT_DIS
11h, Bit 2)
X
0
0
Wake generated when asleep.
Slave SMI# generated when
awake (SMBUS_SMI_STS).
Slave SMI# generated when in
the S0 state (SMBUS_SMI_STS)
None
Interrupt generated
Host SMI# generated
®
6300ESB ICH and it is
Order Number: 300641-004US
Intel
Wake generated
Slave SMI#
generated
(SMBUS_SMI_STS)
Interrupt
generated
Event
®
®
6300ESB ICH
6300ESB ICH—5
Result
November 2007