NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 479

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

10—Intel
Table 373. Offset 02 - 03h: USBSTA—USB Status Register (Sheet 2 of 2)
10.2.3
Table 374. Offset Base + (04 - 05h): USBINTR—Interrupt Enable Register (Sheet
November 2007
Order Number: 300641-004US
15:5
Bits
Bits
Default Value:
Default Value:
2
1
0
4
3
Note: This register enables and disables reporting of the corresponding interrupt to the
Device:
Device:
®
USB Interrupt (USBINT)
Offset:
Offset:
Short Packet Interrupt
6300ESB ICH
USB Error Interrupt
Resume Detect
(RSM_DET)
Scratchpad
Offset Base + (04 - 05h): USBINTR—Interrupt
Enable Register
software. When a bit is set and the corresponding interrupt is active, an interrupt is
generated to the host. Fatal errors (Host Controller Processor Error-bit 4, USBSTS
Register) cannot be disabled by the host controller. Interrupt sources that are disabled
in this register still appear in the Status Register to allow the software to poll for
events.
1 of 2)
Reserved
Enable
29
02 - 03h
0020h
Name
29
Base + (04-05h)
0000h
Name
0 = Software resets this bit to ’0’ by writing a ’1’ to the bit
1 = The Host Controller received a “RESUME” signal from a
0 = Software resets this bit to ’0’ by writing a ’1’ to the bit
1 = Completion of a USB transaction resulted in an error
0 = Software resets this bit to ’0’ by writing a ’1’ to the bit
1 = The Host Controller sets this bit when the cause of an
Reserved.
Scratchpad.
0 = Disabled.
1 = Enabled.
position.
USB device. This is only valid when the Host Controller is
in a global suspend state (bit 3 of Command register =
1).
position.
condition (e.g., error counter underflow). When the TD
on which the error interrupt occurred also had its IOC bit
set, both this bit and Bit ’0’ are set.
position.
interrupt is a completion of a USB transaction whose
Transfer Descriptor had its IOC bit set. Also set when a
short packet is detected (actual length field in TD is less
than maximum length field in TD) and short packet
detection is enabled in that TD.
Description
Description
Attribute:
Attribute:
Function:
Function:
Size:
Size:
X
Rea/Write Clear
16-bit
X
Read/Write
16-bit
Intel
®
6300ESB I/O Controller Hub
Access
Access
R/WC
R/WC
R/WC
R/W
R/W
479
DS