NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 265

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5—Intel
5.20.2.8 Output Slot 6: PCM Playback Center Front Channel
5.20.2.9 Output Slots 7-8: PCM Playback Left and Right Rear
5.20.2.10Output Slot 9: Playback Sub Woofer Channel
5.20.2.11Output Slots 10-11: Reserved
5.20.2.12Output Slot 12: I/O Control
5.20.2.13AC-Link Input Frame (SDIN)
November 2007
Order Number: 300641-004US
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6300ESB ICH
When set up for 6-channel mode, this slot is used for the front center channel. The
format is the same as Slots 3 and 4. When not set up for 6-channel mode, this channel
will always be stuffed with zeros by Intel
Channels
When set up for 4 or 6 channel modes, slots 7 and 8 are used for the rear Left and
Right channels. The format for these two channels are the same as Slots 3 and 4.
When set for 6-channel mode, this slot is used for the Sub Woofer. The format is the
same as Slot three. When not set up for 6-channel mode, this channel will always be
stuffed with zeros by Intel
Output frame slots 10-11 are reserved and are always stuffed with 0s by the Intel
6300ESB ICH AC’97 controller.
Sixteen bits of DAA and GPIO control (output) and status (input) have been directly
assigned to bits on slot 12 in order to minimize latency of access to changing
conditions.
offset 54h and D4h (in the case of a secondary codec) in the modem codec I/O space.
The following rules govern the usage of slot 12.
There are three AC_SDIN lines on the Intel
codecs. Each AC_SDIN pin may have a codec attached. The input frame data streams
correspond to the multiplexed bundles of all digital input data targeting the AC’97
controller. As in the case for the output frame, each AC-link input frame consists of
twelve time slots.
The value of the bits in this slot are the values written to the GPIO control register at
1. Slot 12 is marked invalid by default on coming out of AC-link reset, and will remain
2. A write to offset 54h/D4h in codec I/O space will cause the write data to be
3. After the first write to offset 54h/D4h, slot 12 remains valid for all following frames.
4. Slot 12 will get invalidated after the following events:
invalid until a register write to 54h/D4h.
transmitted on slot 12 in the next frame, with slot 12 marked valid, and the
address/data information to also be transmitted on slots 1 and 2.
The data transmitted on slot 12 is the data last written to offset 54h/D4h. Any
subsequent write to the register will cause the new data to be sent out on the next
frame.
— PCI reset, AC'97 cold reset, warm reset, and hence a wake from S3, S4, or S5.
— Slot 12 will remain invalid until the next write to offset 54h/D4h.
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6300ESB ICH.
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6300ESB ICH.
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6300ESB ICH for use with up to three
Intel
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6300ESB I/O Controller Hub
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