NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 636

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

17.1.8
Table 565. Offset 34h: CAP_PTR—APIC1 Capabilities Pointer (APIC1—D29:F5)
17.1.9
Table 566. Offset 3Ch: ILINE—Interrupt Line (APIC1—D29:F5)
17.1.10 Offset 3Dh: IPIN—Interrupt Pin (APIC1—D29:F5)
Table 567. Offset 3Dh: IPIN—Interrupt Pin (APIC1—D29:F5)
Intel
DS
636
17:0
Bits
Bits
Bits
Default Value:
Default Value:
Default Value:
7:0
7:0
®
6300ESB I/O Controller Hub
Lockable:
Lockable:
Lockable:
Device:
CAP: Capabilities Pointer
Device:
Device:
Offset:
Offset:
Offset:
ILINE: Interrupt Line
IPIN: Interrupt pin
Offset 34h: CAP_PTR—APIC1 Capabilities Pointer
(APIC1—D29:F5)
Offset 3Ch: ILINE—Interrupt Line (APIC1—
D29:F5)
29
34h
50h
No
Name
29
3Ch
00h
No
Name
29
3Dh
00h
No
Name
This register points to the starting offset (50h) of the I/O
APIC1 capabilities range.
This data is not used by the Intel
a scratchpad register to communicate to software the
interrupt line that the interrupt pin is connected to.
The value of 00h indicates that I/O APIC1 does not connect to
PIRQ#.
Power Well:
Power Well:
Power Well:
Description
Description
Description
Attribute:
Attribute:
Attribute:
Function:
Function:
Function:
Size:
Size:
Size:
®
6300ESB ICH. It is used as
5
Read-Only
8-bit
Core
5
Read/Write
8-bit
Core
5
Read-Only
8-bit
Core
Order Number: 300641-004US
Intel
®
6300ESB ICH—17
November 2007
Access
Access
Access
R/W
RO
RO