NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 227

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5—Intel
5.18.4.2.2 Write Policies for Asynchronous DMA
Table 112. Write Policies for Asynchronous DMA
5.18.5
5.18.6
5.18.7
November 2007
Order Number: 300641-004US
®
6300ESB ICH
The Asynchronous DMA engine performs writes for the following reasons.
Data Encoding and Bit Stuffing
See Chapter 8 of the Universal Serial Bus Revision 2.0 Specification.
Packet Formats
See Chapter 8 of the Universal Serial Bus Revision 2.0 Specification.
USB EHCI Interrupts and Error Conditions
Section 4 of the EHCI specification goes into detail on the EHC interrupts and the error
conditions that cause them. All error conditions that the EHC detects may be reported
through the EHCI Interrupt status bits. Only Intel
error-reporting behavior is documented in this section. The EHCI Interrupts Section
must be read first, followed by this section of the EDS to fully comprehend the EHC
interrupt and error-reporting functionality.
Memory Structure
Asynchronous
Queue Head
Overlay
Asynchronous
Queue Head Status
Write
Asynchronous qTD
Status Write
In Data
NOTES:
•
•
•
•
1. The Asynchronous DMA Engine (ADE) will only generate writes after a transaction is executed
2. Status writes are always performed after In Data writes for the same transaction.
on USB.
Based on the EHC’s Buffer sizes and buffer management policies, the Data Buffer
Error may not occur on the Intel
Master Abort and Target Abort responses from Hub Interface on EHC-initiated read
packets will be treated as Fatal Host Errors. The EHC halts when these conditions
are encountered.
The Intel
interrupt threshold as soon as the status for the last complete transaction in the
interrupt interval has been posted in the internal write buffers. The requirement in
the EHCI Specification (that the status is written to memory) is met internally, even
though the write may not be seen on the Hub Interface before the interrupt is
asserted.
Since the Intel
Frame List Rollover interrupt occurs every 1024 milliseconds.
®
6300ESB ICH may assert the interrupts which are based on the
®
(DWORDs
Up to 1297
6300ESB ICH supports the 1024-element Frame List size, the
Size
14
34
3
)
Only the 64-bit addressing format is supported. DWORDs
0C:43h are written.
DWORDs 14:1Fh are written.
DWORDs 04:0Fh are written. PID Code, IOC, Buffer Pointer
(Page 0), and Alt. Next qTD Pointers are re-written with the
original value.
The Intel
DWORD aligned chunks.
®
6300ESB ICH.
®
6300ESB ICH breaks data writes down into 16
®
6300ESB ICH-specific interrupt and
Comments
Intel
®
6300ESB I/O Controller Hub
227
DS