NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 688

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Intel
DS
688
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6300ESB I/O Controller Hub
The Intel
(D30:F0:40h:bit 20) is cleared in order to perform any parity checking as described
below. Good Hub Interface parity is presented to all logic in the Intel
when the bit is set.
To support error reporting on the PCI bus, the Intel
following:
The Intel
Interface. The Intel
Parity Errors
Address parity errors are very serious and may abort further data transfers, depending
upon the direction of the transfer and the setting of the Parity Error Response Enable
bit, as described in the following paragraphs. The Intel
parity for all transactions on both the Hub Interface and PCI buses, for all address and
all bus commands.
When the Intel
Interface packet, it:
When the Intel
following events occur:
The Intel
register (bit 15 of offset 1E-1F).
The Intel
error bit in the Primary Status Register, when all of the following conditions are met:
The Intel
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PERR# and SERR# signals on PCI
Primary status (offset 06-07h) and secondary status registers (offset 1E-1Fh)
Sets the Detected Parity Error bit in the Primary status register (bit 15 of offset 06-
07h) when the address is targeting the device. The bridge devices log address
parity errors independent of the target address.
Generates NMI/SMI (as enabled) and sets the signaled system error bit in the
primary status register (bit 14 of offset 06-07h), when the parity error response bit
in the command register (bit 6 of offset 04-05h) is set and SERR# is enabled.
Attempts to interpret the cycle as best it can, and forwards the cycle with an
address parity error tag to the internal logic, where it aborts internally. When a
device is not enabled to respond to parity errors, it ignores the address parity error
(except for setting the Detected Parity Error bit). When the address targets that
device, the device accepts the cycle and responds as though there was no address
parity error. The cycle is forwarded to PCI with good address parity when the cycle
targets a bridge and it is not enabled to respond to parity errors.
When the parity error response bit is ’0’ in the bridge control register (bit ’0’ of
offset 3E-3F), the address parity errors are ignored. The cycles would be treated as
though no error was observed.
When the parity error response bit is set and the address parity error is observed
on memory cycles, the cycle is accepted as though the address was correct.
Delayed Transactions are established for memory reads and data are posted for
memory writes. The cycles are forwarded to the Hub Interface with correct address
parity.
The SERR# enable bit is set in the primary command register.
The parity error response bit is set in the bridge control register.
The SERR# enable bit is set in the bridge control register.
Port70.7 (I/O register at offset 70h, bit 7) is enabled.
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6300ESB ICH requires that the “Hub Interface Parity Unsupported” bit
6300ESB ICH does not have the PERR# or SERR# pins on the Hub
6300ESB ICH sets the detected parity error bit in the secondary status
6300ESB ICH generates NMI/SMI (as enabled) sets the signaled system
6300ESB ICH generates NMI, if the following conditions are met:
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6300ESB ICH detects an address parity error on the PCI interface, the
6300ESB ICH detects an parity error in the header section of a Hub
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6300ESB ICH is capable of generating NMI, and SMI
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6300ESB ICH implements the
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6300ESB ICH checks address
Order Number: 300641-004US
Intel
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6300ESB ICH
6300ESB ICH—18
November 2007
Address