NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 232

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5.18.9.4 Effect of Resets on Port-Routing Logic
Table 113. Effect of Resets on Port-Routing Logic
5.18.10 USB 2.0 Legacy Keyboard Operation
5.18.11 USB 2.0 EHCI Based Debug Port
Intel
DS
232
®
6300ESB I/O Controller Hub
As mentioned above, the Port Routing logic is implemented in the Suspend power well
so that reenumeration and remapping of the USB ports is not required following
entering and exiting a system sleep state in which the core power is turned off.
The Intel
either a USB UHCI or a USB EHCI port. The description of the legacy keyboard support
is unchanged from USB UHCI (See
The EHC provides the basic ability to generate SMIs on an interrupt event, along with
more sophisticated control of the generation of SMIs.
The Intel
the ability for new debugger software to interact with devices on a USB EHCI port.
High-level restrictions and features are:
Suspend Well Reset
Core Well Reset
D3-to-D0 Reset
HCRESET
3. Configure Flag = 1 and a USB High-speed-capable Device is disconnected.
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•
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and serviced by the associated UHCI driver. The port-routing logic in the
EHC cluster forces the Port Owner bit to 0, indicating that the EHC owns
the unconnected port.
In this case, the USB EHCI Controller is the owner of the port before, and
remains the owner after, the disconnect occurs. The EHCI hardware and
driver handle the disconnection process. The USB UHCI Controller never
sees a device attached.
Must be operational before USB EHCI drivers are loaded.
Must work even when the port is disabled.
Must work even though non-configured port is default-routed to the classic
controller. Note that the Debug Port cannot be used to debug an issue that requires
a classic USB device on Port #0 using the UHCI drivers.
Must allow normal system USB EHCI traffic in a system that may only have one
USB port.
Debug Port device (DPD) must be High-Speed capable and connect to a High-Speed
port on Intel
Debug Port FIFO must always make forward progress (a bad status on USB is
simply presented back to software)
The Debug Port FIFO is only given one USB access per microframe
Reset Event
®
®
6300ESB ICH must support the possibility of a keyboard downstream from
6300ESB ICH supports the elimination of the legacy COM ports by providing
®
6300ESB ICH systems.
cleared (0)
no effect
no effect
cleared (0)
Effect on Configure Flag
Section 5.17.9, “USB Legacy Keyboard
set (1)
no effect
no effect
set (1)
Effect on Port Owner Bits
Order Number: 300641-004US
Intel
®
6300ESB ICH—5
Operation”).
November 2007