NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 371

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

8—Intel
Table 253. Offset FEC0 - EOIR: EOI Register
8.5.6
Table 254. Offset 00h: ID—Identification Register
November 2007
Order Number: 300641-004US
31:8
31:2
27:2
23:1
14:0
Bits
Bits
Default Value:
Default Value:
7:0
15
8
4
6
®
Note: The APIC ID serves as a physical name of the APIC. The APIC bus arbitration ID for the
Device:
Device:
Offset:
Offset:
Redirection Entry Clear
6300ESB ICH
Scratchpad
vector for more than one interrupt input, each of those entries will have the
Remote_IRR bit reset to zero. The interrupt which was prematurely reset will not be
lost because if its input remained active when the Remote_IRR bit is cleared, the
interrupt will be reissued and serviced at a later time.
Offset 00h: ID—Identification Register
APIC is derived from its I/O APIC ID. This register is reset to zero on power up reset.
Reserved
Reserved
Reserved
Reserved
APIC ID
31
FEC0_0040h
N/A
Name
31
00h
00000000h
Name
Reserved. To provide for future expansion, the processor
should always write a value of zero to Bits 31:8.
When a write is issued to this register, the I/O APIC will check
this field, and compare it with the vector field for each entry
in the I/O Redirection Table. When a match is found, the
Remote_IRR bit for that I/O Redirection Entry will be cleared.
Reserved.
Software must program this value before using the APIC.
Reserved.
Scratchpad bit.
Reserved.
Description
Description
Attribute:
Attribute:
Function:
Function:
Size:
Size:
0
Write-Only
32-bit
0
Read/Write
16-bit
Intel
®
6300ESB I/O Controller Hub
Access
Access
R/W
WO
371
DS