NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 711

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

19—Intel
19.5.1.3.1 Receive Buffer Register (RBR)
Table 638. Receive Buffer Register (RBR)
19.5.1.3.2 Transmit Holding Register (THR)
Table 639. Transmit Holding Register (THR)
19.5.1.3.3 Interrupt Enable Register (IER)
November 2007
Order Number: 300641-004US
Note: The use of bit 4 and 5 is different from the register definition of standard 16550.
®
6300ESB ICH
In non-FIFO mode, this register holds the character received by the UART's Receive
Shift Register. If fewer than eight bits are received, the bits are right-justified and the
leading bits are zeroed. Reading the register empties the register and resets the Data
Ready (DR) bit in the Line Status Register to 0. Other (error) bits in the Line Status
Register are not cleared. In FIFO mode, this register latches the value of the data byte
at the top of the FIFO.
This register holds the next data byte to be transmitted. When the Transmit Shift
Register becomes empty, the contents of the Transmit Holding Register are loaded into
the shift register and the transmit data request (TDRQ) bit in the Line Status Register is
set to ’1’.
In FIFO mode, writing to THR puts data to the top of the FIFO. The data at the bottom
of the FIFO is loaded to the shift register when it is empty.
This register enables five types of interrupts which independently activate the int signal
and set a value in the Interrupt Identification Register. Each of the five interrupt types
may be disabled by resetting the appropriate bit of the IER register. Similarly, by
setting the appropriate bits, selected interrupts may be enabled. Receiver time out
interrupt may be configured to be separated from the receive data available interrupt
(using the bit5: COMP) to avoid interrupt controller and DMA controller serving the
receive FIFO at the same time.
Receive Buffer Register
RBR
read only
Transmit Holding Register
THR
write only
Number
Bit Number
Bit
7:0
7:0
Bit Mnemonic
RB[7:0]
Bit Mnemonic
TB[7:0]
Address:
Reset State:
Access:
Data byte received, least significant bit first.
Address:
Reset State:
Access:
Data byte transmitted, least significant bit first.
Base (DLAB=0)
00H
8-bit
Function
Base (DLAB=0)
00H
8 bit
Function
Intel
®
6300ESB I/O Controller Hub
711
DS