NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 799

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

22—Intel
Table 715. PCI-X Interface Timings
November 2007
Order Number: 300641-004US
NOTES:
10.A PCI-X device is permitted to have the minimum values shown for T
11.Device must meet this specification independent of how many outputs switch simultaneously.
1. Refer to
2. Minimum times are measured at the package pin (not a test point).
3. Setup time for point-to-point signals applies to PXREQ[3:0] and PXGNT[3:0] only. All other signals are bused.
4. See timing measurement conditions in
5. PXPCIRST# is asserted and deasserted asynchronously with respect to PXCLKO[4:0].
6. All output drivers must be floated when RSTIN# is active.
7. For purposes of Active/Float timing measurements, the Hi-Z or “off” state is defined to be when the total
8. Setup time applies only when the device is not driving the pin. Devices cannot drive and receive signals at
9. Maximum value is also limited by delay to the first transaction (T
Symbol
T
T
val
T
T
su
Local BUS Specification document.
current delivered through the component pin is less than or equal to the leakage current specification
the same time.
signals after the rising edge of PXPCIRST# must be deasserted no later than two clocks before the first
FRAME# and must be floated no later than one clock before FRAME# is asserted.
In conventional mode, the device must meet the requirements specified in PCI Local Bus Specification,
Revision 2.2, for the appropriate clock frequency.
T
T
T
T
rst-clk
rst-off
T
T
T
T
T
T
T
T
T
pvrh
T
prsu
(ptp)
rrsu
rhfa
rlcx
(ptp)
rhff
val
rrh
prh
off
rst
on
su
h
®
6300ESB ICH
Figure
PXCLKO[4:0] to Signal Valid Delay-bused signals
PXCLKO[4:0] to Signal Valid Delay-point to point
signals
Float to Active Delay
Active to Float Delay
Input Setup Time to PXCLKO[4:0]-Bused signals
Input Setup Time to PXCLKO[4:0]-point to point
Input Hold Time from PXCLKO[4:0]
Reset Active Time after power stable
Reset Active Time after PXCLKO[4:0] stable
Reset Active to output float delay
PXREQ64# to PXPCIRST# setup time
PXPCIRST# to PXREQ64# hold Time
PXPCIRST# high to first configuration access
PXPCIRST# high to first PXFRAME# Assertion
Power valid to PXPCIRST# high
PCI-X initialization pattern to PXPCIRST# setup time
PXPCIRST# to PCI-X initialization pattern hold time
Delay from PXPCIRST# low to PXCLKO[4:0]
frequency change
41. For timing and measurement condition details, refer to the PCI-X Addendum to the PCI
Parameter
Figure
42.
rhfa
). The PCI-X initialization pattern control
val
Min
100
100
0.7
0.7
1.7
1.7
0.5
2
10
10
0
1
0
5
0
0
26
, T
val(ptp)
Max
3.8
3.8
, and T
Intel
40
50
50
7
®
6300ESB I/O Controller Hub
on
clocks
clocks
clocks
Units
ms
μ s
ms
only in PCI-X mode.
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1, 2, 3, 10,
11
1, 2, 3, 10,
11
1, 7, 10,
1, 7,
3, 4,
3,
4
5
5
5,
9
4
6
Notes
11
8
11
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