NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 643

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

17—Intel
17.2.6
Table 578. Offset 00h: ID—Identification Register
17.2.7
November 2007
Order Number: 300641-004US
31:2
27:2
23:0
31:2
23:1
14:8
Bits
Bits
Default Value:
Default Value:
7:0
15
8
4
4
6
Table 579. Offset 01h: VER—Version Register
Note: The APIC ID serves as a physical name of the APIC1. This register is reset to ‘0’ on
Note: Each I/O APIC contains a hardwired Version Register that identifies different
Device:
Device:
®
Offset:
Offset:
Maximum Redirection
6300ESB ICH
Offset 00h: ID—Identification Register
power-up reset.
Offset 01h: VER—Version Register
implementations of APIC and their versions. The maximum redirection entry
information also is in this register to let software know how many interrupts are
supported by this APIC.
Reserved
Reserved
Reserved
Reserved
APIC ID
Version
Entries
29
00h
00000000h
Name
29
01h
00178020h
Name
PRQ
Reserved.
Software must program this value before using the APIC.
Reserved.
Reserved.
This is the entry number (0 being the lowest entry) of the
highest entry in the redirection table. It is equal to the
number of interrupt input pins minus one and is in the range
0 through 239. In the Intel
hardwired to 17h to indicate 24 interrupts.
This bit is set to ’1’ to indicate that this version of the I/O
APIC implements the IRQ Assertion register and allows PCI
devices to write to it to cause interrupts.
Reserved.
This is a version number that identifies the implementation
version. The version number assigned to the Intel
ICH for the I/O (x) APIC is 20h.
Description
Description
Attribute:
Attribute:
Function:
Function:
®
6300ESB ICH
Size:
Size:
5
Read/Write
32-bit
5
Read-Only
32-bit
,
this field is
Intel
®
6300ESB
®
6300ESB I/O Controller Hub
Access
Access
R/W
RO
RO
RO
643
DS