NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 165

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5—Intel
Table 75.
5.11.10.3Read-Only Registers with Write Paths in ALT Access Mode
Table 76.
5.11.11 System Power Supplies, Planes, and Signals
5.11.11.1Power Plane Control with SLP_S3#, SLP_S4# and
5.11.11.2PWROK Signal
November 2007
Order Number: 300641-004US
®
Note: Please review these notes regarding the PWROK signal:
6300ESB ICH
PIC Reserved Bits Return Values
The registers described in
Software will restore these values after returning from a powered down state. These
registers must be handled special by software. When in normal mode, writing to the
base address/count register also writes to the current address/count register.
Therefore, the base address/count must be written first, then the part is put into ALT
access mode and the current address/count register is written.
Register Write Accesses in ALT Access Mode
SLP_S5#
The SLP_S3# output signal may be used to cut power to the system core supply, since
it will only go active for the STR state (typically mapped to ACPI S3). Power must be
maintained to system memory, the Intel
circuits that need to generate Wake signals from the STR state.
Cutting power to the core may be done through the power supply, or by external FETs
to the motherboard. The SLP_S4# or SLP_S5# output signal may be used to cut power
to the system core supply, as well as power to the system memory, since the context of
the system is saved on the disk. Cutting power to the memory may be done through
the power supply, or by external FETs to the motherboard.
The PWROK input should go active based on the core supply voltages becoming valid.
PWROK should go active at least 16 ms after the power is ensured valid.
Address
PIC Reserved Bits
I/O
D0h
08h
OCW2(4:3)
OCW3(4:3)
ICW2(2:0)
ICW4(7:5)
ICW4(3:2)
OCW3(7)
OCW3(5)
ICW4(0)
Table 76
Value Returned
Reflects bit 6
000
000
DMA Status Register for channels 0-3.
DMA Status Register for channels 4-7.
00
00
01
0
0
have write paths to them in ALT access mode.
Register Write Value
®
6300ESB ICH resume well, and to any other
Intel
®
6300ESB I/O Controller Hub
165
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