NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 60

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

3.4
Table 6.
Intel
DS
60
®
6300ESB I/O Controller Hub
PCI-X Interface
PCI-X Interface Signals (Sheet 1 of 4)
PXAD[63:32
PXAD[31:0]
PXDEVSEL#
BE#[3:0]
BE#[7:4]
Name
PXC/
PXC/
]
Type
I/O
I/O
I/O
I/O
I/O
PCI-X Address/Data: These signals are a multiplexed address and
data bus. During the address phase or phases of a transaction, the
initiator drives a physical address on PXAD[31:0]. During the data
phases of a transaction, the initiator drives write data, or the target
drives read data. The Intel
PXAD[31:0] during the address phase of all PCI-X Special Cycles.
PC-X Address/Data: These signals are a multiplexed address and
data bus. This bus provides an additional 32 bits to the PCI-X bus.
During the data phases of a transaction, the initiator drives the upper
32 bits of 64-bit write data, or the target drives the upper 32 bits of
64-bit read data, when PXREQ64# and PXACK64# are both asserted.
When not driven PXAD[63:32] are pulled up to a valid logic level
through external resistors.
NOTE: When not driven PXAD[63:32] are pulled up to a valid logic
Bus Command and Byte Enables: The command and byte enable
signals are multiplexed on the same PCI-X pins. During the address
phase of a transaction, PXC/BE#[3:0] define the bus command.
During the data phase PXC/BE[3:0]# define the Byte Enables.
PXC/BE#[3:0] Command Type
All command encodings not shown are reserved. The Intel
ICH does not decode reserved values, and therefore will not respond
when a PCI-X master generates a cycle using one of the reserved
values.
Bus Command and Byte enables upper 4 bits: These signals are
a multiplexed command field and byte enable field. For both reads
and write transactions, the initiator will drive byte enables for the
PXAD[63:32] data bits on PXC/BE#[7:4] during the data phases
when PXREQ64# and PXACK64# are both asserted. When not driven,
PXC/BE#[7:4] are pulled up to a valid logic level through external
resistors.
Device Select: The Intel
claim a PCI transaction. As an output, the Intel
asserts DEVSEL# when a PCI master peripheral attempts an access
to an internal Intel
the Hub Interface (main memory or AGP). As an input, DEVSEL#
indicates the response to an Intel
on the PCI bus. DEVSEL# is tri-stated from the leading edge of
PXPCIRST#. PXDEVSEL# remains tri-stated by the Intel
ICH until driven by a Target device.
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 1 0
0 1 1 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 1 0
1 1 1 1
level through external resistors.
Interrupt Acknowledge
Special Cycle
I/O Read
I/O Write
Memory Read
Memory Write
Configuration Read
Configuration Write
Memory Read Multiple
Memory Read Line
Memory Write and Invalidate
®
6300ESB ICH address or an address destined for
®
®
6300ESB ICH asserts PXDEVSEL# to
Description
6300ESB ICH will drive all 0’s on
®
6300ESB ICH-initiated transaction
Order Number: 300641-004US
®
Intel
6300ESB ICH
®
6300ESB ICH—3
®
November 2007
®
6300ESB
6300ESB