NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 189

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5—Intel
5.15
5.15.1
5.15.2
5.15.2.1 Standard ATA Emulation
5.15.2.2 48-bit LBA Operation (Logical Block Addressing)
5.15.3
5.15.4
November 2007
Order Number: 300641-004US
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6300ESB ICH
SATA Host Controller (D31:F2)
Overview
The Intel
be independently enabled, tri-stated or driven low. Each interface is supported by an
independent DMA controller.
The Intel
device through a register interface that is equivalent to that presented by a traditional
IDE host adapter. The host software follows existing standards and conventions when
accessing the register interface and follows standard command protocol conventions.
Theory of Operation
The Intel
legacy IDE registers. The behavior of the Command and Control Block registers, PIO
and DMA data transfers, resets, and interrupts are all emulated.
The SATA host controller supports 48-bit LBA through the host-to-device register FIS,
Frame Information Structure, when accesses are performed through writes to the task
file. The SATA host controller will ensure that the correct data is put into the correct
byte of the host-to-device FIS.
There are special considerations when reading from the task file to support 48-bit LBA
operation. Software may need to read all 16 bits. Since the registers are only 8 bits
wide and act as a FIFO, a bit must be set in the device/control register, which is at
offset 3F6h for primary and 376h for secondary (or their native counterparts).
When software clears bit 7 of the control register before performing a read, the last
item written will be returned from the FIFO. When software sets bit 7 of the control
register before performing a read, the first item written will be returned from the FIFO.
Hot Plug Operation
Dynamic hot plug (such as surprise removal) is not supported by the SATA Host
controller. However, using the SPC register configuration bits, and power management
flows, a device may be powered down by software, and the port may then be powered
off, allowing removal and insertion of a new device.
Power Management Operation
Power management of the Intel
operations of the host controller and the SATA wire.
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6300ESB ICH SATA controller features two sets of interface signals that may
6300ESB ICH SATA controller interacts with an attached mass storage
6300ESB ICH contains a set of registers that shadow the contents of the
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6300ESB ICH SATA Controller and ports will cover
Intel
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6300ESB I/O Controller Hub
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