NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 231

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5—Intel
5.18.9.2 Device Connects
5.18.9.3 Device Disconnects
November 2007
Order Number: 300641-004US
®
6300ESB ICH
The Intel
of Port #0. When in this mode, the Enhanced Host Controller is the owner of Port #0.
Section 4.2 of the EHCI Specification describes the details of handling Device Connects.
There are four general scenarios that are summarized below. See
“Offset CAPLENGTH + 40 - 43h: CONFIGFLAG—Configure Flag
Section 4.2 of the EHCI Specification describes the details of handling Device Connects.
There are three general scenarios that are summarized below. See
“Offset CAPLENGTH + 40 - 43h: CONFIGFLAG—Configure Flag
1. Configure Flag = 0 and a USB Full-speed/Low-speed -only Device is connected
2. Configure Flag = 0 and an USB High-speed-capable Device is connected
3. Configure Flag = 1 and a USB Full-speed/Low-speed-only Device is connected
4. Configure Flag = 1 and an USB High-speed-capable Device is connected
1. Configure Flag = 0 and the device is disconnected.
2. Configure Flag = 1 and a USB Full-speed/Low-speed-capable Device is
In this case, the USB UHCI Controller is the owner of the port both before
and after the connect occurs. The EHC (except for the port-routing logic)
never sees the connect occur. The UHCI driver handles the connection and
initialization process.
In this case, the USB UHCI Controller is the owner of the port both before
and after the connect occurs. The EHC (except for the port-routing logic)
never sees the connect occur. The UHCI driver handles the connection and
initialization process. Since the USB UHCI Controller does not perform the
high-speed chirp handshake, the device operates in compatible mode.
In this case, the USB EHCI Controller is the owner of the port before the
connect occurs. The EHCI driver handles the connection and performs the
port reset. After the reset process completes, the EHC hardware has
cleared (not set) the Port Enable bit in the EHC’s PORTSC register. The
EHCI driver then writes a 1 to the Port Owner bit in the same register,
causing the USB UHCI Controller to see a connect event and the EHC to
see an “electrical” disconnect event. The UHCI driver and hardware handle
the connection and initialization process from that point on. The EHCI
driver and hardware handle the perceived disconnect.
In this case, the USB EHCI Controller is the owner of the port before, and
remains the owner after, the connect occurs. The EHCI driver handles the
connection and performs the port reset. After the reset process completes,
the EHC hardware has set the Port Enable bit in the EHC’s PORTSC register.
The port is functional at this point. The USB UHCI Controller continues to
see an unconnected port.
In this case, the USB UHCI Controller is the owner of the port both before
and after the disconnect occurs. The EHC (except for the port-routing
logic) never sees a device attached. The UHCI driver handles disconnection
process.
disconnected.
In this case, the USB UHCI Controller is the owner of the port before the
disconnect occurs. The disconnect is reported by the USB UHCI Controller
®
6300ESB ICH also allows the USB Debug Port traffic to be routed in and out
Intel
Register”.
Register”.
®
6300ESB I/O Controller Hub
Section 11.2.2.8,
Section 11.2.2.8,
231
DS