NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 809
NHE6300ESB S L7XJ
Manufacturer Part Number
NHE6300ESB S L7XJ
Description
Manufacturer
Intel
Datasheet
1.NHE6300ESB_S_L7XJ.pdf
(848 pages)
Specifications of NHE6300ESB S L7XJ
Lead Free Status / RoHS Status
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22—Intel
Table 723. AC’97 Timing
Table 724. LPC Timing
Table 725. Miscellaneous Timings
November 2007
Order Number: 300641-004US
t
Sym
t
t15
t15
t15
t15
t15
t15
t15
t15
t16
t16
t16
t16
t16
t16
setup
Sy
Sy
m
m
hold
t
0
1
2
3
4
5
6
7
0
1
2
3
4
5
co
LAD[3:0] Valid Delay from PCICLK Rising
LAD[3:0] Output Enable Delay from PCICLK Rising
LAD[3:0] Float Delay from PCICLK Rising
LAD[3:0] Setup Time to PCICLK Rising
LAD[3:0] Hold Time from PCICLK Rising
LDRQ[1:0]# Setup Time to PCICLK Rising
LDRQ[1:0]# Hold Time from PCICLK Rising
LFRAME# Valid Delay from PCICLK Rising
SERIRQ Setup Time to PCICLK Rising
SERIRQ Hold Time from PCICLK Rising
RI# Pulse Width
SPKR Valid Delay from CLK14 Rising
SERR# Active to NMI Active
IGNNE# Inactive from FERR# Inactive
ACSDIN[2:0] Setup to Falling Edge of BITCLK
ACSDIN[2:0] Hold from Falling Edge of BITCLK
ACSYNC, ACSDOUT valid delay from rising edge of BITCLK
®
6300ESB ICH
Parameter
Parameter
Parameter
Min
Min
12
Min
2
2
7
0
0
2
7
0
2
10
10
Max
Max
200
200
230
Max
11
28
12
15
Intel
RTCCLK
Units
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
®
6300ESB I/O Controller Hub
Notes
Notes
Note
s
Figure 65
Figure 65
Figure 65
Figure 45
Figure 49
Figure 47
Figure 46
Figure 46
Figure 46
Figure 46
Figure 45
Figure 46
Figure 46
Figure 48
Figure 45
Fig
Fig
Fig
809
DS
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