NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 35

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Contents—Intel
November 2007
Order Number: 300641-004US
109 Read Policies for Periodic DMA ................................................................................. 224
110 Write Policies for Periodic DMA ................................................................................. 225
111 Read Policies for Asynchronous DMA ......................................................................... 226
112 Write Policies for Asynchronous DMA ........................................................................ 227
113 Effect of Resets on Port-Routing Logic ....................................................................... 232
114 USB Debug Port Behavior ........................................................................................ 233
115 Quick Protocol ....................................................................................................... 239
116 Send/Receive Byte Protocol without PEC ................................................................... 239
117 Send/Receive Byte Protocol with PEC ........................................................................ 240
118 Write Byte/Word Protocol without PEC ...................................................................... 240
119 Write Byte/Word Protocol with PEC ........................................................................... 240
120 Read Byte/Word Protocol without PEC ....................................................................... 242
121 Read Byte/Word Protocol with PEC ........................................................................... 242
122 Process Call Protocol without PEC ............................................................................. 243
123 Process Call Protocol with PEC ................................................................................. 243
124 Block Read/Write Protocol without PEC...................................................................... 245
125 Block Read/Write Protocol with PEC .......................................................................... 245
126 I
127 Block Write-Block Read Process Call Protocol With/Without PEC .................................... 248
128 Enable for SMBALERT# ........................................................................................... 250
129 Enables for SMBus Slave Write and SMBus Host Events ............................................... 250
130 Enables for the Host Notify Command ....................................................................... 251
131 Slave Write Cycle Format ........................................................................................ 252
132 Slave Write Registers ............................................................................................. 253
133 Command Types .................................................................................................... 253
134 Read Cycle Format ................................................................................................. 254
135 Data Values for Slave Read Registers........................................................................ 255
136 Host Notify Format ................................................................................................. 257
137 Features Supported by Intel
138 AC’97 Signals ........................................................................................................ 262
139 Input Slot 1 Bit Definitions ...................................................................................... 267
140 Output Tag Slot 0 .................................................................................................. 269
141 AC-link State during PXPCIRST# .............................................................................. 273
142 PCI Devices and Functions....................................................................................... 276
143 Fixed I/O Ranges Decoded by Intel
144 Variable I/O Decode Ranges .................................................................................... 281
145 Memory Decode Ranges from CPU Perspective ........................................................... 283
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PCI Configuration Registers (D30:F0)
Offset 00 - 01h: VID—Vendor ID Register (HUB-PCI—D30:F0)
Offset 02 - 03h: DID—Device ID Register (HUB-PCI—D30:F0)
Offset 04 - 05h: CMD—Command Register (HUB-PCI—D30:F0)
Offset 06 - 07h: PD_STS—Primary Device Status Register
Offset 08h: RID—Revision Identification Register (HUB-PCI—D30:F0)
Offset 0Ah: SCC—Sub-Class Code Register (HUB-PCI—D30:F0)
Offset 0Bh: BCC—Base-Class Code Register (HUB-PCI—D30:F0)
Offset 0Dh: PMLT—Primary Master Latency Timer Register (HUB-PCI—D30:F0)
Offset 0Eh: HEADTYP—Header Type Register
Offset 18h: PBUS_NUM—Primary Bus Number Register
Offset 19h: SBUS_NUM—Secondary Bus Number Register
Offset 1A: SUB_BUS_NUM—Subordinate Bus Number Register (HUB-PCI—D30:F0)
Offset 1Bh: SMLT—Secondary Master Latency Timer Register (HUB-PCI—D30:F0)
Offset 1Ch: IOBASE—I/O Base Register (HUB-PCI—D30:F0)
Offset 1Dh: IOLIM—I/O Limit Register (HUB-PCI—D30:F0)
Offset 1E - 1Fh: SECSTS—Secondary Status Register (HUB-PCI—D30:F0)
Offset 20 - 21h: MEMBASE—Memory Base Register (HUB-PCI—D30:F0)
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C Block Read Protocol .......................................................................................... 246
®
6300ESB ICH
®
6300ESB ICH .............................................................. 258
®
6300ESB I/O Controller Hub ................................ 278
....................................................................... 287
(HUB-PCI—D30:F0)................................. 292
(HUB-PCI—D30:F0)................... 292
(HUB-PCI—D30:F0)............... 293
(HUB-PCI—D30:F0)............... 290
.......................................... 295
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Intel
........................... 291
®
6300ESB I/O Controller Hub
........................ 297
..................... 295
.............. 292
.......... 294
........ 293
DS
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