NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 350

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

8.2.3
Table 222. DMABASE_CC—DMA Base and Current Count Registers
8.2.4
Table 223. DMACMD—DMA Command Register
Intel
DS
350
Bits
Bits
Default Value:
Default Value:
7:0
7:5
1:0
I/O Address:
I/O Address:
4
3
2
®
6300ESB I/O Controller Hub
Lockable:
Lockable:
Device:
Device:
DMA Group Arbitration
Address bits [23:16]
DMA Channel Group
DMA Low Page (ISA
DMAMEM_LP—DMA Memory Low Page Registers
DMACMD—DMA Command Register
Reserved
Reserved
Reserved
Priority
Enable
31
Ch. #0 = 87h; Ch. #1 =
83h, Ch. #2 = 81h; Ch.
#3 = 82h, Ch. #5 = 8Bh
Ch. #6 = 89h, Ch. #7 =
8Ah
Undefined
No
Name
31
Ch. #0-3 = 08h
Ch. #4-7 = D0h
Undefined
No
Name
This register works in conjunction with the DMA controller's
Current Address Register to define the complete 24-bit
address for the DMA channel. This register remains static
throughout the DMA transfer. Bit 16 of this register is ignored
when in 16 bit I/O count by words mode as it is replaced by
the bit 15 shifted out from the current address register.
Reserved. Must be 0.
Each channel group is individually assigned either fixed or
rotating arbitration priority. At part reset, each group is
initialized in fixed priority.
0 = Fixed priority to the channel group
1 = Rotating priority to the group.
Reserved. Must be zero.
Both channel groups are enabled following part reset.
0 = Enable the DMA channel group.
1 = Disable. Disabling channel group 4-7 also disables
Reserved. Must be zero.
channel group 0-3, which is cascaded through channel 4.
Power Well:
Power Well:
Description
Description
Attribute:
Attribute:
Function:
Function:
Size:
Size:
0
Read/Write
8-bit
Core
0
Write-Only
8-bit
Core
Order Number: 300641-004US
Intel
®
6300ESB ICH—8
November 2007
Access
Access
R/W
WO
WO