NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 328

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NHE6300ESB S L7XJ

Manufacturer Part Number
NHE6300ESB S L7XJ
Description
Manufacturer
Intel
Datasheet

Specifications of NHE6300ESB S L7XJ

Lead Free Status / RoHS Status
Compliant
Table 202. Offset D0h - D3h: GEN_CNTL—General Control Register (LPC I/F—
Intel
DS
328
19:1
16:1
10:9
Bits
Default Value:
5:3
17
14
13
12
11
8
5
8
7
6
®
6300ESB I/O Controller Hub
Lockable:
Device:
Offset:
APIC_EN: APIC Enable
ALTACC_EN: Alternate
Access Mode Enable
IRQ1LEN: Keyboard
IRQ12 Latch Enable
IRQ1 Latch Enable
IRQ12LEN: Mouse
Coprocessor Error
MMT_ADDR_SEL
COPR_ERR_EN:
MMT_ADDR_EN
SCRATCHPAD
D31:F0)
Reserved
Reserved
Reserved
Reserved
(Sheet 2 of 3)
Enable
31
D0h - D3h
00000080h
No
Name
These bits are provided for possible future use.
When set to 1, this bit enables the Intel
decode the High Performance Event Timer Memory Address
Range selected by bits 16:15 below.
This 2-bit field selects 1 of 4 possible memory address ranges
for the High Performance Event Timer functionality. The
encodings are:
Bits [16:15]
Reserved.
0 = FERR# will not generate IRQ13 nor IGNNE#.
1 = When FERR# is low, the Intel
0 = IRQ1 will bypass the latch.
1 = The active edge of IRQ1 will be latched and held until a
0 = IRQ12 will bypass the latch.
1 = The active edge of IRQ12 will be latched and held until a
Reserved.
0 = Disables internal I/O (x) APIC.
1 = Enables the internal I/O (x) APIC and its address decode.
Reserved.
0 = Alt Access Mode Disabled (default). ALT access mode
1 = Alt Access Mode Enable.
Reserved.
00
01
10
11
IRQ13 internally and holds it until an I/O write to port
F0h. It will also drive IGNNE# active.
port 60h read.
port 60h read.
allows reads to otherwise unreadable registers and writes
otherwise unwritable registers.
Memory Address Range
FED0_0000h - FED0_03FFh
FED0_1000h - FED0_13FFh
FED0_2000h - FED0_23FFh
FED0_3000h - FED0_33FFh
Power Well:
Description
Attribute:
Function:
Size:
®
6300ESB ICH generates
0
Read/Write
32-bit
Core
®
6300ESB ICH to
Order Number: 300641-004US
Intel
®
6300ESB ICH—8
November 2007
Access
R/W
R/W
R/W
R/W
R/W

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