NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 403

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

8—Intel
Table 290. GPE0_STS—General Purpose Event 0 Status Register (Sheet 3 of 3)
November 2007
Order Number: 300641-004US
Bits
Default Value:
I/O Address:
5
4
3
2
1
0
Lockable:
®
Device:
6300ESB ICH
Status (THRM_STS)
Thermal Interrupt
Thermal Interrupt
Override Status
(THRMOR_STS)
AC97_STS
USB2_STS
USB1_STS
Reserved
31
PMBASE + 28h
(ACPI PGPE0_BLK)
00000000h
No
Name
This bit will be set to 1 by when the codecs are attempting to
wake the system and the PME events for the codecs are
armed for wakeup. A PME is armed by programming the
appropriate PMEE bit in the Power Management Control and
Status register at bit 8 of offset 54h in each AC’97 function.
0 = Software clears this bit by writing a 1 to the bit position.
1 = Set by hardware when the codecs are attempting to wake
This bit is not affected by a hard reset caused by a CF9h
write.
0 = Software clears this bit by writing a 1 to the bit position.
1 = Set by hardware when USB UHCI Controller 2 needs to
0 = Software clears this bit by writing a 1 to the bit position.
1 = Set by hardware when USB UHCI Controller 1 needs to
Reserved.
0 = Software clears this bit by writing a 1 to the bit position.
1 = This bit is set by hardware anytime a thermal over-ride
0 = Software clears this bit by writing a 1 to the bit position.
1 = Set by hardware anytime the THRM# signal is driven
the system. The AC97_STS bit gets set only from the
following two cases:
1. The PMEE bit for the function is set, and the AC-link bit
clock has been shut and the routed AC_SDIN line is high
(for audio, when routing is disabled, no wake events are
allowed).
2. For modem, when audio routing is disabled, the wake
event is an OR of all AC_SDIN lines. When routing is
enabled, the wake event for modem is the remaining
non-routed AC_SDIN line), or o GPI Status Change
Interrupt bit (NABMBAR + 30h, bit 0) is 1.
cause a wake. Wake event will be generated when the
corresponding USB2_EN bit is set.
cause a wake. Wake event will be generated when the
corresponding USB1_EN bit is set.
condition occurs and starts throttling the processor’s
clock at the THRM_DTY ratio. This will not cause an
SMI#, SCI, or wake event.
active as defined by the THRM_POL bit. Additionally,
when the THRM_EN bit is set, the setting of the
THRM_STS bit will also generate a power management
event (SCI or SMI#).
Power Well:
Description
Attribute:
Function:
Size:
0
Read/Write Clear
32-bit
Resume
Intel
®
6300ESB I/O Controller Hub
Access
R/WC
R/WC
R/WC
R/WC
R/WC
403
DS