NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 492

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

11.1.12 Offset 3Ch: Interrupt Line
Table 390. Offset 3Ch: Interrupt Line
11.1.13 Offset 3Dh: Interrupt Pin
Table 391. Offset 3Dh: Interrupt Pin
11.1.14 Offset 50h: PCI Power Management Capability ID
Table 392. Offset 50h: PCI Power Management Capability ID
Intel
DS
492
Bits
Bits
Bits
Default Value:
Default Value:
Default Value:
7:0
7:0
7:0
®
6300ESB I/O Controller Hub
Device:
Device:
Device:
Offset:
Offset:
Offset:
Interrupt Line
Interrupt Pin
29
3Ch
00h
Name
29
3Dh
04h
Name
29
50h
01h
Name
This data is not used by the Intel
a scratchpad register to communicate to software the
interrupt line that the interrupt pin is connected to.
The value of 04h indicates that the USB EHCI function within
the Intel
the fourth interrupt pin from the device–NTD# in PCI terms.
The value of 04h in function 7 is required because the PCI
specification does not recognize more than four interrupts,
and older APM-based OSs require that each function within a
multi-function device has a different Interrupt Pin Register
value.
Internally the USB EHCI controller uses PIRQ[H]#.
A value of 01h indicates that this is a PCI Power Management
capabilities field.
®
6300ESB ICH’s multi-function USB device will drive
Description
Description
Description
Attribute:
Attribute:
Attribute:
Function:
Function:
Function:
Size:
Size:
Size:
®
6300ESB ICH. It is used as
7
Read/Write
8-bit
7
Read-Only
8-bit
7
Read-Only
8-bit
Order Number: 300641-004US
Intel
®
6300ESB ICH—11
November 2007
Access
Access
Access
R/W
RO