NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 28

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

20
Intel
DS
28
®
6300ESB I/O Controller Hub
19.6
19.7
19.8
Serial ATA Controller Registers
(D31:F2)737
20.1
Logical Device 7 (07H): Port 60/64 Emulation...................................................... 724
19.6.1 Feature List ......................................................................................... 724
19.6.2 Overview ............................................................................................. 724
Serial IRQ....................................................................................................... 725
19.7.1 Timing Diagrams For SIU_SERIRQ Cycle .................................................. 725
Configuration .................................................................................................. 728
19.8.1 Configuration Port Address Selection ....................................................... 728
19.8.2 Primary Configuration Address Decoder ................................................... 728
19.8.3 SIU Configuration Registers Summary ..................................................... 730
PCI Configuration Registers (SATA–D31:F2) ........................................................ 737
20.1.1 Offset 00 - 01h: VID—Vendor ID Register (SATA—D31:F2) ........................ 738
20.1.2 Offset 02 - 03h: DID—Device ID Register (SATA—D31:F2)......................... 739
20.1.3 Offset 04h - 05h: CMD—Command Register (SATA–D31:F2)....................... 739
20.1.4 Offset 06 - 07h: STS—Device Status Register
20.1.5 Offset 09h: PI—Programming Interface (SATA–D31:F2)............................. 742
20.1.6 Offset 0Ah: SCC—Sub Class Code (SATA–D31:F2) .................................... 742
20.1.7 Offset 0Bh: BCC—Base Class Code (SATA–D31:F2) ................................... 743
20.1.8 Offset 0Dh: MLT—Master Latency Timer (SATA–D31:F2) ............................ 743
20.1.9 Offset 10h - 13h: PCMD_BAR—Primary Command Block
20.1.10Offset 14h - 17h: PCNL_BAR—Primary Control Block Base
20.1.11Offset 18h - 1Bh: SCMD_BAR—Secondary Command Block
20.1.12Offset 14h - 17h: SCNL_BAR—Secondary Control Block
20.1.13Offset 20h - 23h: BAR—Legacy Bus Master Base Address
20.1.14Offset 2Ch - 2Dh: SVID—Subsystem Vendor ID
20.1.15Offset 2Eh - 2Fh: SID—Subsystem ID (SATA–D31:F2)............................... 747
20.1.16Offset 34h: CAP—Capabilities Pointer Register
20.1.17Offset 3Ch: INTR_LN—Interrupt Line Register
20.1.18Offset 3Dh: INTR_PN—Interrupt Pin Register
19.5.1.3 Internal Register Descriptions ................................................... 710
19.5.1.4 FIFO Operation ....................................................................... 723
19.6.2.1 Port 60H Emulation (SCR60) ..................................................... 725
19.6.2.2 Port 64H Emulation (SCR64) ..................................................... 725
19.7.1.1 SIU_SERIRQ Cycle Control ....................................................... 726
19.7.1.2 SIU_SERIRQ Data Frame.......................................................... 727
19.7.1.3 Stop Cycle Control................................................................... 727
19.7.1.4 Latency.................................................................................. 728
19.7.1.5 EOI/ISR Read Latency.............................................................. 728
19.7.1.6 Reset and Initialization............................................................. 728
19.8.2.1 Entering the Configuration State ............................................... 729
19.8.2.2 Exiting the Configuration State.................................................. 729
19.8.2.3 Configuration Sequence ........................................................... 729
19.8.2.4 Configuration Mode ................................................................. 729
19.8.3.1 Global Control/Configuration Registers [00h — 2Fh]..................... 731
19.8.3.2 Logical Device Configuration Registers [30h — FFh] ..................... 731
(SATA–D31:F2) .................................................................................... 741
Base Address Register (SATA–D31:F2) .................................................... 744
Address Register (SATA–D31:F2)............................................................ 744
Base Address Register (IDE D31:F1) ....................................................... 745
Base Address Register (IDE D31:F1) ....................................................... 745
Register (SATA–D31:F2)........................................................................ 746
(SATA–D31:F2) .................................................................................... 746
(SATA–D31:F2) .................................................................................... 747
(SATA–D31:F2) .................................................................................... 747
(SATA–D31:F2) .................................................................................... 748
Intel
Order Number: 300641-004US
®
6300ESB ICH—Contents
November 2007